Sfoglia per Autore
Simple and Accurate Model for the Propagation Delay in MCML Gates
file da validare2023-01-01 Giustolisi, G; Scotti, G; Palumbo, G
A Biasing Approach to design Ultra-Low-Power Standard-Cell-Based Analog Building Blocks for Nanometer SoCs
2022-01-01 Centurelli, F.; Giustolisi, G.; Pennisi, S.; Scotti, G.
Design Methodology of the Output Power Stage of a Step-Down DC-DC Converter
2022-01-01 Bella, Angelo Lucio; Giustolisi, Gianluca; Rosa, Manuela La; Sicurella, Giovanni
Analysis and Comparison in the Energy-Delay Space of Nanometer CMOS One-Bit Full-Adders
2022-01-01 Giustolisi, Gianluca; Palumbo, Gaetano
A Novel Clock Gating Approach for the Design of Low-Power Linear Feedback Shift Registers
2022-01-01 Giustolisi, G; Mita, R; Palumbo, G; Scotti, G
Hybrid Full Adders: Optimized Design, Critical Review and Comparison in the Energy-Delay Space
2022-01-01 Giustolisi, G; Palumbo, G
Design of three-stage OTAs from settling-time and slew-rate constraints
2021-01-01 Giustolisi, G.; Palumbo, G.
A gm/ID-Based Design Strategy for IoT and Ultra-Low-Power OTAs with Fast-Settling and Large Capacitive Loads
2021-01-01 Giustolisi, Gianluca; Palumbo, Gaetano
Behavioral model of silicon photo-multipliers suitable for transistor-level circuit simulation
2021-01-01 Giustolisi, G.; Finocchiaro, P.; Pappalardo, A.; Palumbo, G.
Design of Three-Stage OTA Based on Settling-Time Requirements Including Large and Small Signal Behavior
2021-01-01 Giustolisi, G.; Palumbo, G.
Efficient design strategy for optimizing the settling time in three-stage amplifiers including small-and large-signal behavior
2021-01-01 Giustolisi, G.; Palumbo, G.
Design of CMOS three-stage amplifiers for near-to-minimum settling-time
2021-01-01 Giustolisi, Gianluca; Palumbo, Gaetano
Optimized Charge Pump with Clock Booster for Reduced Rise Time or Silicon Area
2019-01-01 Ballo, A.; Grasso, A. D.; Giustolisi, G.; Palumbo, G.
Autonomous Energy-Efficient Wireless Sensor Network Platform for Home/Office Automation
2019-01-01 Abella, C. S.; Bonina, S.; Cucuccio, A.; D’Angelo, S.; Giustolisi, G.; Grasso, A. D.; Imbruglia, A.; Mauro, G. S.; Nastasi, G. A. M.; Palumbo, G.; Pennisi, S.; Sorbello, G.; Scuderi., A.
Design of CMOS OTAs with Settling-Time Constraints
2019-01-01 Giustolisi, Gianluca; Palumbo, Gaetano
In-Depth Analysis of Pole-Zero Compensations in CMOS Operational Transconductance Amplifiers
2019-01-01 Giustolisi, Gianluca; Palumbo, Gaetano
A Clock Boosted Charge Pump with Reduced Rise Time
2019-01-01 Ballo, Andrea; Giustolisi, Gianluca; Grasso, Alfio Dario; Palumbo, Gaetano
Class-AB CMOS output stages suitable for low-voltage amplifiers in nanometer technologies
2019-01-01 Giustolisi, Gianluca; Palumbo, Gaetano; Pennisi, Salvatore
High-dimensional dynamics in a single-transistor oscillator containing Feynman-Sierpiński resonators: Effect of fractal depth and irregularity
2018-01-01 Minati, Ludovico; Frasca, Mattia; Giustolisi, Gianluca; Oświȩcimka, Paweł; Drozdz, Stanisław; Ricci, Leonardo
Bessel-like compensation of three-stage operational transconductance amplifiers
2018-01-01 Giustolisi, Gianluca; Palumbo, Gaetano
Legenda icone
- file ad accesso aperto
- file disponibili sulla rete interna
- file disponibili agli utenti autorizzati
- file disponibili solo agli amministratori
- file sotto embargo
- nessun file disponibile