Sfoglia per Autore
Multiobjective End-to-End Design Space Exploration of Parameterized DNN Accelerators
2023-01-01 Russo, Enrico; Palesi, Maurizio; Patti, Davide; Monteleone, Salvatore; Ascia, Giuseppe; Catania, Vincenzo
MEDEA: A Multi-objective Evolutionary Approach to DNN Hardware Mapping
2022-01-01 Russo, E.; Palesi, M.; Monteleone, S.; Patti, D.; Ascia, G.; Catania, V.
Combined Application of Approximate Computing Techniques in DNN Hardware Accelerators
2022-01-01 Russo, Enrico; Palesi, Maurizio; Patti, Davide; Lahdhiri, Habiba; Monteleone, Salvatore; Ascia, Giuseppe; Catania, Vincenzo
Exploiting the Approximate Computing Paradigm with DNN Hardware Accelerators
2022-01-01 Russo, Enrico; Palesi, Maurizio; Monteleone, Salvatore; Patti, Davide; Lahdhiri, Habiba; Ascia, Giuseppe; Catania, Vincenzo
LAMBDA: An Open Framework for Deep Neural Network Accelerators Simulation
2021-01-01 Russo, E.; Palesi, M.; Monteleone, S.; Patti, D.; Ascia, G.; Catania, V.
DNN Model Compression for IoT Domain Specific Hardware Accelerators
file da validare2021-01-01 Russo, E.; Palesi, M.; Monteleone, S.; Patti, D.; Mineo, A.; Ascia, G.; Catania, V.
Exploiting data resilience in wireless network-on-chip architectures
2020-01-01 Ascia, G.; Catania, V.; Monteleone, S.; Palesi, M.; Patti, D.; Jose, J.; Salerno, V. M.
Improving inference latency and energy of network-on-chip based convolutional neural networks through weights compression
file da validare2020-01-01 Ascia, G.; Catania, V.; Jose, J.; Monteleone, S.; Palesi, M.; Patti, D.
Improving Inference Latency and Energy of DNNs through Wireless Enabled Multi-Chip-Module-based Architectures and Model Parameters Compression
2020-01-01 Ascia, G.; Catania, V.; Mineo, A.; Monteleone, S.; Palesi, M.; Patti, D.
Approximate Wireless Networks-on-Chip
2019-01-01 Ascia, Giuseppe; Catania, Vincenzo; Monteleone, Salvatore; Palesi, Maurizio; Patti, Davide; Jose, John
Analyzing networks-on-chip based deep neural networks
2019-01-01 Ascia, G.; Catania, V.; Monteleone, S.; Palesi, M.; Patti, D.; Jose, J.
Networks-on-Chip based Deep Neural Networks Accelerators for IoT Edge Devices
2019-01-01 Ascia, G.; Catania, V.; Monteleone, S.; Palesi, M.; Patti, D.; Jose, J.
Improving energy consumption of NoC based architectures through approximate communication
2018-01-01 Ascia, Giuseppe; Catania, Vincenzo; Monteleone, Salvatore; Palesi, Maurizio; Patti, Davide; Jose, John
Exploiting antenna directivity in wireless NoC architectures
2016-01-01 Mineo, A; Palesi, Maurizio; Ascia, Giuseppe; Catania, Vincenzo
Making android apps data-leak-safe by data flow analysis and code injection
2016-01-01 Ascia, Giuseppe; Catania, Vincenzo; Di Natale, R; Fornaia, ANDREA FRANCESCO; Mongiovi', Misael; Monteleone, Salvatore; Pappalardo, Giuseppe; Tramontana, EMILIANO ALESSIO
On-Chip Communication Energy Reduction through Reliability Aware Adaptive Voltage Swing Scaling
2016-01-01 Mineo, A; Palesi, Maurizio; Ascia, Giuseppe; Pande, P; Catania, Vincenzo
Runtime Tunable Transmitting Power Technique in mm-Wave WiNoC Architectures
2016-01-01 Mineo, A; Palesi, Maurizio; Ascia, Giuseppe; Catania, Vincenzo
A closed loop power manager for transmission power control in wireless network-on-chip architectures
2015-01-01 Rusli, M. S.; Mineo, A; Palesi, Maurizio; Ascia, Giuseppe; Catania, Vincenzo; Yee, O. C.; Marsono, M. N.
A closed loop transmitting power self-calibration scheme for energy efficient WiNoC architectures
2015-01-01 Mineo, A; Rusli M., S; Palesi, Maurizio; Ascia, Giuseppe; Catania, Vincenzo; Marsono, M. N.
Coupling routing algorithm and data encoding for low power Networks on Chip
2015-01-01 Palesi, Maurizio; Patti, Davide; Ascia, Giuseppe; Panno, Daniela Giovanna Anna; Catania, Vincenzo
| Titolo | Data di pubblicazione | Autore(i) | File |
|---|---|---|---|
| Multiobjective End-to-End Design Space Exploration of Parameterized DNN Accelerators | 1-gen-2023 | Russo, Enrico; Palesi, Maurizio; Patti, Davide; Monteleone, Salvatore; Ascia, Giuseppe; Catania, Vincenzo | |
| MEDEA: A Multi-objective Evolutionary Approach to DNN Hardware Mapping | 1-gen-2022 | Russo, E.; Palesi, M.; Monteleone, S.; Patti, D.; Ascia, G.; Catania, V. | |
| Combined Application of Approximate Computing Techniques in DNN Hardware Accelerators | 1-gen-2022 | Russo, Enrico; Palesi, Maurizio; Patti, Davide; Lahdhiri, Habiba; Monteleone, Salvatore; Ascia, Giuseppe; Catania, Vincenzo | |
| Exploiting the Approximate Computing Paradigm with DNN Hardware Accelerators | 1-gen-2022 | Russo, Enrico; Palesi, Maurizio; Monteleone, Salvatore; Patti, Davide; Lahdhiri, Habiba; Ascia, Giuseppe; Catania, Vincenzo | |
| LAMBDA: An Open Framework for Deep Neural Network Accelerators Simulation | 1-gen-2021 | Russo, E.; Palesi, M.; Monteleone, S.; Patti, D.; Ascia, G.; Catania, V. | |
| DNN Model Compression for IoT Domain Specific Hardware Accelerators | 1-gen-2021 | Russo, E.; Palesi, M.; Monteleone, S.; Patti, D.; Mineo, A.; Ascia, G.; Catania, V. | file da validare |
| Exploiting data resilience in wireless network-on-chip architectures | 1-gen-2020 | Ascia, G.; Catania, V.; Monteleone, S.; Palesi, M.; Patti, D.; Jose, J.; Salerno, V. M. | |
| Improving inference latency and energy of network-on-chip based convolutional neural networks through weights compression | 1-gen-2020 | Ascia, G.; Catania, V.; Jose, J.; Monteleone, S.; Palesi, M.; Patti, D. | file da validare |
| Improving Inference Latency and Energy of DNNs through Wireless Enabled Multi-Chip-Module-based Architectures and Model Parameters Compression | 1-gen-2020 | Ascia, G.; Catania, V.; Mineo, A.; Monteleone, S.; Palesi, M.; Patti, D. | |
| Approximate Wireless Networks-on-Chip | 1-gen-2019 | Ascia, Giuseppe; Catania, Vincenzo; Monteleone, Salvatore; Palesi, Maurizio; Patti, Davide; Jose, John | |
| Analyzing networks-on-chip based deep neural networks | 1-gen-2019 | Ascia, G.; Catania, V.; Monteleone, S.; Palesi, M.; Patti, D.; Jose, J. | |
| Networks-on-Chip based Deep Neural Networks Accelerators for IoT Edge Devices | 1-gen-2019 | Ascia, G.; Catania, V.; Monteleone, S.; Palesi, M.; Patti, D.; Jose, J. | |
| Improving energy consumption of NoC based architectures through approximate communication | 1-gen-2018 | Ascia, Giuseppe; Catania, Vincenzo; Monteleone, Salvatore; Palesi, Maurizio; Patti, Davide; Jose, John | |
| Exploiting antenna directivity in wireless NoC architectures | 1-gen-2016 | Mineo, A; Palesi, Maurizio; Ascia, Giuseppe; Catania, Vincenzo | |
| Making android apps data-leak-safe by data flow analysis and code injection | 1-gen-2016 | Ascia, Giuseppe; Catania, Vincenzo; Di Natale, R; Fornaia, ANDREA FRANCESCO; Mongiovi', Misael; Monteleone, Salvatore; Pappalardo, Giuseppe; Tramontana, EMILIANO ALESSIO | |
| On-Chip Communication Energy Reduction through Reliability Aware Adaptive Voltage Swing Scaling | 1-gen-2016 | Mineo, A; Palesi, Maurizio; Ascia, Giuseppe; Pande, P; Catania, Vincenzo | |
| Runtime Tunable Transmitting Power Technique in mm-Wave WiNoC Architectures | 1-gen-2016 | Mineo, A; Palesi, Maurizio; Ascia, Giuseppe; Catania, Vincenzo | |
| A closed loop power manager for transmission power control in wireless network-on-chip architectures | 1-gen-2015 | Rusli, M. S.; Mineo, A; Palesi, Maurizio; Ascia, Giuseppe; Catania, Vincenzo; Yee, O. C.; Marsono, M. N. | |
| A closed loop transmitting power self-calibration scheme for energy efficient WiNoC architectures | 1-gen-2015 | Mineo, A; Rusli M., S; Palesi, Maurizio; Ascia, Giuseppe; Catania, Vincenzo; Marsono, M. N. | |
| Coupling routing algorithm and data encoding for low power Networks on Chip | 1-gen-2015 | Palesi, Maurizio; Patti, Davide; Ascia, Giuseppe; Panno, Daniela Giovanna Anna; Catania, Vincenzo |
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