In this communication we propose an approach for the design of CMOS amplifiers with settling-time constraints. The design approach ensures that the settling time constraint is satisfied under any statistical fluctuation of process or design parameters. The approach is validated through the design example of a three-stage CMOS amplifier.
Design of CMOS OTAs with Settling-Time Constraints
Giustolisi, Gianluca;Palumbo, Gaetano
2019-01-01
Abstract
In this communication we propose an approach for the design of CMOS amplifiers with settling-time constraints. The design approach ensures that the settling time constraint is satisfied under any statistical fluctuation of process or design parameters. The approach is validated through the design example of a three-stage CMOS amplifier.File in questo prodotto:
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C054 - Design of CMOS OTAs with Settling-Time Constraints.pdf
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