In this paper we explore the effects of pole-zero compensation in the settling performance of operational transconductance amplifiers (OTAs). We carry out the analysis by exploiting a proficient technique that provides an in-depth comprehension of the time domain behavior from the contour plots of the Normalized Settling Time. Starting from the case of a single-pole amplifier, we show the conditions upon which the settling time is degraded by the slow time constant set by the pole-zero doublet. Then, we extend these results to two-pole amplifiers and provide a useful design equation. Design examples of a two-stage and a single-Miller three-stage OTAs confirm the validity of the proposed theoretical models.

In-Depth Analysis of Pole-Zero Compensations in CMOS Operational Transconductance Amplifiers

Gianluca Giustolisi
Primo
;
Gaetano Palumbo
Ultimo
2019-01-01

Abstract

In this paper we explore the effects of pole-zero compensation in the settling performance of operational transconductance amplifiers (OTAs). We carry out the analysis by exploiting a proficient technique that provides an in-depth comprehension of the time domain behavior from the contour plots of the Normalized Settling Time. Starting from the case of a single-pole amplifier, we show the conditions upon which the settling time is degraded by the slow time constant set by the pole-zero doublet. Then, we extend these results to two-pole amplifiers and provide a useful design equation. Design examples of a two-stage and a single-Miller three-stage OTAs confirm the validity of the proposed theoretical models.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.11769/369423
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