A circuit comprises a power supply oscillator (10) coupled to one side of a galvanic barrier (GB) to supply thereto an electric supply signal. The power supply oscillator is configured to be alternatively turned on and off as a function of a PWM drive signal (PWMA) applied thereto. A receiver circuit block (12) coupled to the galvanic barrier (GB) receives therefrom a PWM power control signal (PWMB). A signal reconstruction network (26, 28, 30) between the receiver circuit block (12) and the power supply oscillator (10) provides to the power supply oscillator (10) a PWM drive signal (PWMA) reconstructed from the PWM power control signal (PWMB). The signal reconstruction network (26, 28, 30) comprises a PLL circuit block (26) coupled to the receiver circuit block (12) and configured to lock to the PWM control signal (ckSAMPLE) from the receiver circuit block (12). The PLL circuit block (26) comprises a PLL loop (262, 264, 266) sensitive to the PWM drive signal (PWMA) applied to the power supply oscillator (10). The PLL loop (262, 264, 266) is configured (266) to be opened as a result of the power supply oscillator (10) being turned off.
A galvanic isolation circuit and system, corresponding method
A. Parisi;N. Greco;E. Ragonese;G. Palmisano
2019-01-01
Abstract
A circuit comprises a power supply oscillator (10) coupled to one side of a galvanic barrier (GB) to supply thereto an electric supply signal. The power supply oscillator is configured to be alternatively turned on and off as a function of a PWM drive signal (PWMA) applied thereto. A receiver circuit block (12) coupled to the galvanic barrier (GB) receives therefrom a PWM power control signal (PWMB). A signal reconstruction network (26, 28, 30) between the receiver circuit block (12) and the power supply oscillator (10) provides to the power supply oscillator (10) a PWM drive signal (PWMA) reconstructed from the PWM power control signal (PWMB). The signal reconstruction network (26, 28, 30) comprises a PLL circuit block (26) coupled to the receiver circuit block (12) and configured to lock to the PWM control signal (ckSAMPLE) from the receiver circuit block (12). The PLL circuit block (26) comprises a PLL loop (262, 264, 266) sensitive to the PWM drive signal (PWMA) applied to the power supply oscillator (10). The PLL loop (262, 264, 266) is configured (266) to be opened as a result of the power supply oscillator (10) being turned off.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.