An experimental study on the optimization of two-stage OTAs using different output stages and compensation techniques is presented. Optimization tries to maximize GBW for a given quiescent current consumption, and to this aim transistors are operating in weak inversion. A test chip prototype including 8 different two-stage OTA configurations has been fabricated in a standard 0.5-μm CMOS technology. Measurement results validate the benefits of the optimization technique employed in different design scenarios.
GBW Optimization in Two-Stage OTAs Operating in Weak Inversion
Grasso A. D.Primo
;Palumbo G.;Pennisi S.
2023-01-01
Abstract
An experimental study on the optimization of two-stage OTAs using different output stages and compensation techniques is presented. Optimization tries to maximize GBW for a given quiescent current consumption, and to this aim transistors are operating in weak inversion. A test chip prototype including 8 different two-stage OTA configurations has been fabricated in a standard 0.5-μm CMOS technology. Measurement results validate the benefits of the optimization technique employed in different design scenarios.File in questo prodotto:
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