MINEO, ANDREA
MINEO, ANDREA
INGEGNERIA ELETTRICA ELETTRONICA E INFORMATICA
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Improving Energy Efficiency in Wireless Network-on-Chip Architectures
2017-01-01 Catania, Vincenzo; Mineo, Andrea; Monteleone, Salvatore; Palesi, Maurizio; Patti, Davide
Improving Inference Latency and Energy of DNNs through Wireless Enabled Multi-Chip-Module-based Architectures and Model Parameters Compression
2020-01-01 Ascia, G.; Catania, V.; Mineo, A.; Monteleone, S.; Palesi, M.; Patti, D.
Low Power Techniques for Future Network-on-Chip Architectures
2017-01-14 Mineo, Andrea
| Titolo | Data di pubblicazione | Autore(i) | File |
|---|---|---|---|
| Improving Energy Efficiency in Wireless Network-on-Chip Architectures | 1-gen-2017 | Catania, Vincenzo; Mineo, Andrea; Monteleone, Salvatore; Palesi, Maurizio; Patti, Davide | |
| Improving Inference Latency and Energy of DNNs through Wireless Enabled Multi-Chip-Module-based Architectures and Model Parameters Compression | 1-gen-2020 | Ascia, G.; Catania, V.; Mineo, A.; Monteleone, S.; Palesi, M.; Patti, D. | |
| Low Power Techniques for Future Network-on-Chip Architectures | 14-gen-2017 | Mineo, Andrea |