Area-optimized sub-fF offset trimming circuit for capacitive MEMS interfaces

This paper presents a trimming correction technique to calibrate the offset in capacitive readout circuits of MEMS sensors. The technique relies on a N-bit digital voltage divider which allows to implement an equivalent variable capacitor with sub-femto Farad step variations. To reduce area occupation, a hybrid approach entailing both resistive and capacitor voltage dividers is introduced. Design equations showing the tradeoff between linearity and area occupation versus relative mismatch of capacitors and resistors are derived. Design examples are reported showing a reduction of area occupation greater than 60% while preserving linearity performance.