In this communication we propose a simple and well-defined approach for the design of fast settling amplifiers suitable for switched capacitors circuits. The design is based on a settling-time oriented compensation that makes the phase of the closed-loop amplifier to be linearly related to the frequency, thus emulating the behavior of an ideal delay, like in a Bessel filter. The design and the simulation of a three-stage amplifier in a 65-nm CMOS process validate the proposed settling-time oriented approach.
|Titolo:||Settling-time oriented OTA design through the approximation of the ideal delay|
|Data di pubblicazione:||2018|
|Appare nelle tipologie:||4.1 Contributo in Atti di convegno|