A new very low-voltage topology to implement MOS current mode logic (MCML) XOR gates is proposed in this paper. Instead of stacking several level oftransistors to implement a two inputs XOR gate, a p-type differential pair is used to steer the current in n-type differential pairs through current mirrors. The proposed topology allows to reduce the minimum supply voltage of MCML XOR gates while guaranteeing a fully current mode behavior as in the conventional XOR gate. The proposed topology has been compared against the conventional and triple tail MCML XOR gates. Simulation results referring to a 40 n m CMOS technology for VDD=1 V confirm that the XOR gate presented in this work exhibits a lower propagation delay than the previously published low voltage MCML XOR gate. Furthermore both theoretical analysis and simulation results in a 40 n m process show that the proposed topology is able to work with a VDD as low as 0.65 V whereas state of the art topologies are not usable below 0.8 V.

A Novel Very Low Voltage Topology to implement MCML XOR Gates

Palumbo, Gaetano;
2018

Abstract

A new very low-voltage topology to implement MOS current mode logic (MCML) XOR gates is proposed in this paper. Instead of stacking several level oftransistors to implement a two inputs XOR gate, a p-type differential pair is used to steer the current in n-type differential pairs through current mirrors. The proposed topology allows to reduce the minimum supply voltage of MCML XOR gates while guaranteeing a fully current mode behavior as in the conventional XOR gate. The proposed topology has been compared against the conventional and triple tail MCML XOR gates. Simulation results referring to a 40 n m CMOS technology for VDD=1 V confirm that the XOR gate presented in this work exhibits a lower propagation delay than the previously published low voltage MCML XOR gate. Furthermore both theoretical analysis and simulation results in a 40 n m process show that the proposed topology is able to work with a VDD as low as 0.65 V whereas state of the art topologies are not usable below 0.8 V.
9781538653869
File in questo prodotto:
File Dimensione Formato  
08430320-A Novel Very Low Voltage Topology.pdf

non disponibili

Tipologia: Versione Editoriale (PDF)
Dimensione 200.36 kB
Formato Adobe PDF
200.36 kB Adobe PDF   Visualizza/Apri

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/20.500.11769/361605
Citazioni
  • ???jsp.display-item.citation.pmc??? ND
  • Scopus 4
  • ???jsp.display-item.citation.isi??? 2
social impact