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EnglishNew circuit solutions able to operate under sub-1V supplies must be developed by analog designer to counteract the low intrinsic gain and limited rejection to common-mode and power supply disturbances offered by nanometer CMOS technologies. In this communication, an approach originally developed as a common-mode control loop for body-driven amplifiers, is exploited in the active load of a source-coupled pair to remarkably improve its small-signal performance. Simulations on a 65-nm design supplied from 0.75V show a nominal increase in differential DC gain, CMRR and PSRR of 20 dB, 29 dB and 32 dB, respectively, as compared to the standard solution.
| Titolo: | CMOS differential stage with improved DC Gain, CMRR and PSRR performance | |
| Autori interni: | ||
| Data di pubblicazione: | 2019 | |
| Handle: | http://hdl.handle.net/20.500.11769/385000 | |
| ISBN: | 978-1-7281-0996-1 | |
| Appare nelle tipologie: | 4.1 Contributo in Atti di convegno |
File in questo prodotto:
http://hdl.handle.net/20.500.11769/385000
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