he study on the impact of the PCB parasitics on the performances of a SiC three-level Vienna rectifier addressing electric vehicle on-board battery charger applications was recently published [1]. High switching frequency and small rise/fall times drive for high efficiency, but due to the increased time derivative of the current, PCB parasitic effects caused a change of the design approach moving from a two layer to a four layer PCB design to avoid ringing and over- undershoot scenarios with the risk of damaging the semiconductor devices. Considerations related to an optimization of the PCB concern the EMI problems that are of high interest especially in the automotive field [2] where it can be included the application object of this study. This work shows an extension of the previous investigation [1] in optimizing the layout of the four layer PCB further by means of simulating mode conversion in the gate source wiring for the three phases and studying the impact of some layout parameters. Results obtained with different PCB model are compared for different design iterations.

Analysis of the gate driver stray inductance in a Vienna rectifier through parametric Electromagnetic simulations

Francesco Gennaro;Giuseppe Aiello;Mario Cacciato
;
2020-01-01

Abstract

he study on the impact of the PCB parasitics on the performances of a SiC three-level Vienna rectifier addressing electric vehicle on-board battery charger applications was recently published [1]. High switching frequency and small rise/fall times drive for high efficiency, but due to the increased time derivative of the current, PCB parasitic effects caused a change of the design approach moving from a two layer to a four layer PCB design to avoid ringing and over- undershoot scenarios with the risk of damaging the semiconductor devices. Considerations related to an optimization of the PCB concern the EMI problems that are of high interest especially in the automotive field [2] where it can be included the application object of this study. This work shows an extension of the previous investigation [1] in optimizing the layout of the four layer PCB further by means of simulating mode conversion in the gate source wiring for the three phases and studying the impact of some layout parameters. Results obtained with different PCB model are compared for different design iterations.
2020
978-3-8007-5225-6
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.11769/411778
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