This paper presents behavioral model for a N-stage charge pump valid over a wide clock frequency range. The hardware description language used to develop the model is the Verilog-AMS, which allows simulations of both analog and digital systems, such as systems on a chip and nonvolatile memories. The proposed code allows a huge reduction of time-to-market constraint, since it reduces simulation time while maintaining a good agreement with transistor-level simulations. Model validation has been carried out by the comparison between different charge pumps implemented in SPICE (ideal components) and Verilog-AMS and simulated with Spectre. The model has been also validated on a regulated charge pump. The achieved results have confirmed the validity of the developed description in terms of simulation time and accuracy.
A General Behavioral Model of Charge Pump DC-DC converters
Ballo A.;Grasso A. D.
Co-primo
;Palumbo G.
2020-01-01
Abstract
This paper presents behavioral model for a N-stage charge pump valid over a wide clock frequency range. The hardware description language used to develop the model is the Verilog-AMS, which allows simulations of both analog and digital systems, such as systems on a chip and nonvolatile memories. The proposed code allows a huge reduction of time-to-market constraint, since it reduces simulation time while maintaining a good agreement with transistor-level simulations. Model validation has been carried out by the comparison between different charge pumps implemented in SPICE (ideal components) and Verilog-AMS and simulated with Spectre. The model has been also validated on a regulated charge pump. The achieved results have confirmed the validity of the developed description in terms of simulation time and accuracy.File | Dimensione | Formato | |
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