The aim of this paper is to suitably exploit the measurements of gate-source voltages to extract useful information relative to the crosstalk phenomena that can occur in SiC MOSFETs half-bridge converters. In particular, this work underlines how the measurement of the gate-source voltage in the complementary power device of the half-bridge can be significantly compromised by the parasitic elements related to the printed circuit board layout and device packaging, providing not reliable results, which do not reflect the real trend of the induced voltages. A more reliable measure of the gate-source voltage has been obtained by exploiting on the same power converter topology a suitable four terminal package device including an additional Kelvin source pin, which has been left open to exclude from the voltage measure the voltage drops related to parasitic inductive terms present in the power circuit. Thanks to this solution, it is possible to evaluate a more realistic behavior of the gate-source voltage trend during the switching transients of power devices composing the half-bridge converter, allowing a more detailed analysis of the undesired and uncontrolled cross-conduction and gate-oxide stresses. Simulations results achieved with a suitable analytical model and experimental tests performed on a half-bridge converter based on 1200V, 70A SiC MOSFETs devices confirm the effectiveness of this approach.

Gate-Source Voltage Analysis for Switching Crosstalk Evaluation in SiC MOSFETs Half-Bridge Converters

Salvo L.;Pulvirenti M.;Sciacca A. G.;Scelba G.;Cacciato M.
2021-01-01

Abstract

The aim of this paper is to suitably exploit the measurements of gate-source voltages to extract useful information relative to the crosstalk phenomena that can occur in SiC MOSFETs half-bridge converters. In particular, this work underlines how the measurement of the gate-source voltage in the complementary power device of the half-bridge can be significantly compromised by the parasitic elements related to the printed circuit board layout and device packaging, providing not reliable results, which do not reflect the real trend of the induced voltages. A more reliable measure of the gate-source voltage has been obtained by exploiting on the same power converter topology a suitable four terminal package device including an additional Kelvin source pin, which has been left open to exclude from the voltage measure the voltage drops related to parasitic inductive terms present in the power circuit. Thanks to this solution, it is possible to evaluate a more realistic behavior of the gate-source voltage trend during the switching transients of power devices composing the half-bridge converter, allowing a more detailed analysis of the undesired and uncontrolled cross-conduction and gate-oxide stresses. Simulations results achieved with a suitable analytical model and experimental tests performed on a half-bridge converter based on 1200V, 70A SiC MOSFETs devices confirm the effectiveness of this approach.
2021
978-1-7281-5135-9
Cross-talk Monitoring
Gate Source Probing
Kelvin Source
Phase-Leg Configuration
SiC MOSFET
File in questo prodotto:
File Dimensione Formato  
ECCE2021_Gate-Source_Voltage_Analysis_for_Switching_Crosstalk_Evaluation_in_SiC_MOSFETs_Half-Bridge_Converters.pdf

solo gestori archivio

Tipologia: Versione Editoriale (PDF)
Dimensione 897.2 kB
Formato Adobe PDF
897.2 kB Adobe PDF   Visualizza/Apri

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.11769/526287
Citazioni
  • ???jsp.display-item.citation.pmc??? ND
  • Scopus 4
  • ???jsp.display-item.citation.isi??? 1
social impact