Triple Clock Boosted Voltage Multiplier: A Design Strategy to Heavily Reduce Rise Time

This paper introduces a Dickson voltage multiplier topology which includes a triple voltage booster to achieve better performance in terms of speed at the same maximum output voltage and silicon-occupied area. The proposed solution comes with an optimization design strategy that maximizes the advantages given by the applied clock boosting technique. The comparison with the conventional design demonstrates the effectiveness of the proposed solution. Such comparison is carried out by simulating the two topologies by using the 65-nm CMOS technology provided by STMicroelectronics.