Nanometer CMOS Clocked Storage Elements: Optimization Techniques, Comparison and Novel Energy-Efficient Design Solutions

Clocked storage elements are among the most important elements in the design of digital systems, such as microprocessors, since they allow to synchronize and regulate the entire flow of digital data within the system. With the aim of obtaining conspicuous performance increments at each process generation, dimensional scaling has been supported by the reduction of the number of logic stages within each pipeline stage. Therefore, an increasing impact of the timing overhead due to clocked storage elements on the clock period can be observed. Moreover, the continuous increase in energy consumption has become the major concern limiting the speed performances of VLSI integrated circuits, insomuch as, even for high-speed systems, designs undergo a power limited regime and the achievement of energy-efficiency becomes the primary target. The topics of energy-efficient design, analysis, comparison and selection of suitable clocked storage elements topologies for applications in nanometer technologies have been the focus of the research activity carried out by the candidate in pursuit of the Ph.D. degree. The aim of this thesis is to provide a deep understanding of the challenges relative to clocked storage elements design and selection when including all the above mentioned aspects, as well as to propose novel energy-efficient solutions at the transistor- and micro-architectural design levels. The basic theoretical foundations are provided to set the stage for the comprehension of analyses and results. Exhaustive methodologies are presented and many analytical derivations are included, since they allow to gain an insight on the main dependencies of relevant parameters on circuital properties. Finally, several results, which have been derived by carrying out extensive simulation analyses and measurements on an integrated chip prototype are reported to emphasize the practical perspective of the work.