Power Loop Parasitics Impact on Paralleled Silicon Carbide MOSFETs

This paper investigates the dynamic characterization of parallel connected SiC MOSFETs performed considering half-bridge converter structure. An innovative aspect of the work on this topic is the investigation of the effects of the power loop parasitic elements. In particular, it is highlighted that mismatch issues arise because of the DC-link contribution even when the layout of the converter is symmetric and the paralleled devices have similar static characteristics. Simulations and experiments have pointed out that the mismatch issue is caused by the internal parasitic elements between the DC-Link terminals.