Hardware Implementation of a Fault Recovery Protocol Compliant with Interbus-S Standard

In this paper the authors present an hardware implementation of Interbus-S protocol sub-blocks which include an extension of the protocol that manage the fault recovery capability. The feult recovery protocol is based on the definition of a novel device called Master/Slave able to recover any occurring fault. The Master/Slave device will be implemented into an FPGA chip. It contains the physical layer and a portion of data link and they are described through VHDL language. Gate level simulations are carried out to verify the functionality and compatibility with Interbus-S of the Fault Recovery Protocol. © 2004 IEEE.