A Fully-Synthesizable And-Or-Invert-Based Pseudo-Dynamic Voltage Comparator

A Fully-Synthesizable Pseudo-Dynamic Voltage Comparator (PDVC), based on AOI (And-Or-Invert) standardcells is presented. The topology exploits AOI gates to reduce the clock-to-output delay and Power-Delay-Product with respect to the other conventional Dynamic Voltage Comparators (DVCs) in literature, and, its operating principle is described in detail at transistor level. The overall performance of the circuit is assessed, referring to a 45 nm CMOS technology, considering three different supply voltages: 0.6V, 0.3V and 0.15V, along the entire Non-Rail-to-Rail input common-mode range (ICMR). The results demonstrate the strong advantages of the proposed PDVC, in terms of 2.5 x to 38 x higher speed and 2.9 x to 25.7 x lower PDP, with respect to the other conventional Non-Rail-to-Rail ICMR DVCs in literature, even considering Ultra-Low supply voltages down to 0.15V.