A Low-Power 4x Multiplier Based on Current-Reuse Complementary Push-Push Doublers

This paper presents a frequency quadrupler targeting the 60-GHz band, designed in a 28-nm bulk CMOS technology. The proposed architecture consists of two cascaded doublers based on common-gate (CG) stage with capacitive cross-coupling and integrated LC tanks, enabling efficient generation of the fourth harmonic of the 15-GHz input signal. The 60-GHz signal is further increased by a pseudo-differential cross-coupled cascode amplifier, while an output buffer is added for on-wafer measurement purposes. Electromagnetic (EM) and circuit-level simulations show effective input/output matching and a maximum power conversion gain of −2.6 dB at 0-dBm input power. The total power consumption is as low as 16 mW with a 0.9-V supply, resulting in a total efficiency (ηTOT) of approximately 3.15%.