In this paper, the impact of variations on the most representative pulsed flip-flops topologies is comparatively evaluated in 65-nm CMOS. The analysis explicitly considers fundamental sources of variations such as process, voltage, temperature and clock slope. For each FF topology, the variations are statistically evaluated through Monte Carlo simulations and they explicitly include the non-negligible impact of layout parasitics.
Variability Budget in Pulsed Flip-Flops
PALUMBO, Gaetano;
2015-01-01
Abstract
In this paper, the impact of variations on the most representative pulsed flip-flops topologies is comparatively evaluated in 65-nm CMOS. The analysis explicitly considers fundamental sources of variations such as process, voltage, temperature and clock slope. For each FF topology, the variations are statistically evaluated through Monte Carlo simulations and they explicitly include the non-negligible impact of layout parasitics.File in questo prodotto:
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