Comparative Analysis of the Robustness of Master-Slave Flip-Flops against Variations

In this paper, the variation of performance and robustness against hold time violations are investigated for various representative Master-Slave flip-flops. The analysis explicitly considers process, voltage, temperature, clock slope variations. Their relative contribution to the overall variability budget is also studied. Results in 65-nm CMOS technology provide a quantitative understanding of the importance of each contribution, while including the very important impact of layout parasitics. From a design perspective, results are useful to preliminarily define the variability budget for min/max-delay violations (e.g., to preliminarily set the corresponding clock uncertainty in automated design flows), identify the most critical variability contributions, and select the most suitable flip-flop for a targeted application.