In this communication, an ultra-compact I-V nanometer MOS model is used to predict the dynamic characteristics (propagation delay and rise/fall times) of CMOS inverter and more complex stacked-transistor gates. Simulations reveal typical errors within 1-3% (always less than 6%) for the simple inverter case and within 4-8% (always less than 11%) in the case of stacked-transistor gates.
Logic Gates Dynamic Modeling by Means of an Ultra-Compact MOS Model
GIUSTOLISI, Gianluca;PALUMBO, Gaetano
2012-01-01
Abstract
In this communication, an ultra-compact I-V nanometer MOS model is used to predict the dynamic characteristics (propagation delay and rise/fall times) of CMOS inverter and more complex stacked-transistor gates. Simulations reveal typical errors within 1-3% (always less than 6%) for the simple inverter case and within 4-8% (always less than 11%) in the case of stacked-transistor gates.File in questo prodotto:
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