The paper proposes a parallel VLSI architecture to implement the data link layer in HSLANs and MANs. The proposed architecture is then assessed by modelling it through a Petri Network simulation tool. The results obtained show that the data link layer implemented according to the proposed architecture can effectively work at a data rate up to 150 Mbps.
A parallel VLSI architecture for high speed protocol implementation
CATANIA, Vincenzo;CAVALIERI, Salvatore
;L. VITA
1990-01-01
Abstract
The paper proposes a parallel VLSI architecture to implement the data link layer in HSLANs and MANs. The proposed architecture is then assessed by modelling it through a Petri Network simulation tool. The results obtained show that the data link layer implemented according to the proposed architecture can effectively work at a data rate up to 150 Mbps.File in questo prodotto:
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