IRIS
MARANO, DAVIDE
 Distribuzione geografica
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Continente #
EU - Europa 52
AS - Asia 2
AF - Africa 1
Totale 55
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Nazione #
IT - Italia 49
FR - Francia 2
VN - Vietnam 2
CI - Costa d'Avorio 1
FI - Finlandia 1
Totale 55
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Città #
Vittoria 20
Catania 18
Aci Catena 10
Hanoi 2
Abidjan 1
Helsinki 1
Paris 1
Totale 53
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Nome #
Single miller capacitor frequency compensation techniques: Theoretical comparison and critical review, file dfe4d22e-611b-bb0a-e053-d805fe0a78d9 7
Front-End electronics for the Muon Portal Project, file dfe4d227-a764-bb0a-e053-d805fe0a78d9 4
The Muon Portal Double Tracker for the Inspection of Travelling Containers, file dfe4d227-2e11-bb0a-e053-d805fe0a78d9 3
Low-power high-speed rail-to-rail LCD output buffer with dual-path push–pull operation and quiescent current control, file dfe4d227-9aa0-bb0a-e053-d805fe0a78d9 3
A New Compact Low-Power High-Speed Rail-to-Rail Class-B Buffer for LCD Applications, file dfe4d227-9eb1-bb0a-e053-d805fe0a78d9 3
A New Accurate Analytical Expression for the SiPM Transient Response to Single Photons, file dfe4d227-b38c-bb0a-e053-d805fe0a78d9 3
A New Advanced RNMC Technique with Dual-Active Current and Voltage Buffers for Low-Power High-Load Three-Stage Amplifiers, file 88c47e9f-9879-40ac-bfb0-4710d1144c6f 2
Fabrication, characterization and testing of silicon photomultipliers for the Muon Portal Project, file dfe4d227-1b80-bb0a-e053-d805fe0a78d9 2
Metodologia di progettazione di OTA a tre stadi di guadagno CMOS sottosoglia, file dfe4d227-6e02-bb0a-e053-d805fe0a78d9 2
Fabrication, Characterization and Testing of Silicon Photomultipliers for the Muon Portal Project, file dfe4d227-85b5-bb0a-e053-d805fe0a78d9 2
Step-Response Optimization Techniques for Low-Power Three-Stage Operational Amplifiers Driving Large Capacitive Loads, file dfe4d227-9650-bb0a-e053-d805fe0a78d9 2
A New Enhanced PSPICE Implementation of the Equivalent Circuit Model of SiPM Detectors, file dfe4d227-9a16-bb0a-e053-d805fe0a78d9 2
A New Advanced RNMC Technique with Dual-Active Current and Voltage Buffers for Low-Power High-Load Three-Stage Amplifiers, file dfe4d227-ba49-bb0a-e053-d805fe0a78d9 2
A New Accurate Analytical Expression for the SiPM Transient Response to Single Photons, file 4a5f2580-da45-4a1a-9840-1bf58291746b 1
Step-Response Optimization Techniques for Low-Power Three-Stage Operational Amplifiers Driving Large Capacitive Loads, file 505f71d9-94a3-4d1d-89a6-d791ea0733fb 1
Low-Power Dual-Active Class-AB Buffer Amplifier with Self-Biasing Network for LCD Column Drivers, file dfe4d227-9de4-bb0a-e053-d805fe0a78d9 1
Reversed Double Pole-Zero Cancellation Frequency Compensation Technique for Three-Stage Amplifiers, file dfe4d227-9e1a-bb0a-e053-d805fe0a78d9 1
A 0.003-mm2 50-mW Three-Stage Amplifier Driving 10-nF with 2.7-MHz GBW, file dfe4d227-a350-bb0a-e053-d805fe0a78d9 1
195-nW 120-dB Subthreshold CMOS OTA Driving up to 200 pF and Occupying only 4.4·10-3 mm2, file dfe4d227-a401-bb0a-e053-d805fe0a78d9 1
Enhanced Analytical Model and Output Dynamic Response of SiPM-Based Electronic Read-Outs, file dfe4d227-a7eb-bb0a-e053-d805fe0a78d9 1
An Efficient RNM Compensation Topology with Voltage Buffer and Nulling Resistors for Large-Capacitive-Load Three-Stage OTAs, file dfe4d227-a90f-bb0a-e053-d805fe0a78d9 1
Improved Power-Efficient RNMC Technique with Voltage Buffer and Nulling Resistors for Low-Power High-Load Three-Stage Amplifiers, file dfe4d227-ac58-bb0a-e053-d805fe0a78d9 1
A High-Speed Low-Power Output Buffer Amplifier for Large-Size LCD Applications, file dfe4d227-b06e-bb0a-e053-d805fe0a78d9 1
Improved Low-Power High-Speed Buffer Amplifier with Slew-Rate Enhancement for LCD Applications, file dfe4d227-b0f8-bb0a-e053-d805fe0a78d9 1
Analytical Figure of Merit Evaluation of RNMC Networks for Low-Power Three-Stage OTAs, file dfe4d227-b375-bb0a-e053-d805fe0a78d9 1
Self-Biased Dual-Path Push-Pull Output Buffer Amplifier Topology for LCD Driver Applications, file dfe4d227-ba7a-bb0a-e053-d805fe0a78d9 1
A Novel Low-Power High-Speed Rail-to-Rail Class-B Buffer Amplifier for LCD Output Drivers, file dfe4d227-c39d-bb0a-e053-d805fe0a78d9 1
Design Methodology of Subthreshold Three-Stage CMOS OTAs Suitable for Ultra-Low-Power Low-Area and High Driving Capability, file dfe4d227-dcda-bb0a-e053-d805fe0a78d9 1
Symbolic factorization methodology for multistage amplifier transfer functions, file dfe4d227-ddef-bb0a-e053-d805fe0a78d9 1
Improved Reversed Nested Miller Frequency Compensation Technique With Voltage Buffer and Resistor, file dfe4d227-e097-bb0a-e053-d805fe0a78d9 1
Three-stage single-miller CMOS OTA driving 10 nF with 1.46-MHz GBW, file dfe4d229-9bae-bb0a-e053-d805fe0a78d9 1
Totale 55
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Categoria #
all - tutte 80
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 80
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2022/202346 0 2 0 0 1 9 4 27 1 2 0 0
2023/20245 0 0 0 0 1 2 0 1 0 1 0 0
Totale 55