Lumped Parameter Modelling of Internal Temperature Dynamics in Multichip Power Modules

This study assesses a lumped parameter modelling strategy for the fast response, layer-resolved prediction of the thermal 􀏐ield within the die of a selected power module device. A benchmark 1D lumped parameter model was initially de􀏐ined, providing a simple description of the thermal 􀏐ield through the identi􀏐ication of a low number of lumped parameters but retaining information only on the junction temperature. A re􀏐ined analytical model was therefore developed by adding the internal temperature nodes at the interfaces between the device layers. Thus, with a moderate increase of the lumped parameters, the model was able to predict the thermal behaviour of the inner layers of the die, which is the fundamental information required by reliability analysis. The set of model parameters were determined from the step-response thermal impedances of the power module, simulated by means of a numerical model purposely assessed under a boundary condition of forced liquid cooling. The lumped parameter identi􀏐ication consisted in a curve 􀏐itting procedure calculating the couples of thermal resistance and conductance. Both models were implemented in Matlab- Simulink, and simulated in order to predict the thermal response of the device to conditions of both step-wise and alternating current power inputs.