Layout Impact on Current Sharing in SiC Power Modules: Modeling and Experimental Validation

A model for the analysis of the current imbalance in a SiC power module, including parallel-connected devices, is presented in this paper. The model, based on the real geometry, relied on Ansys for layout analysis, both for the power module and for the printed circuit board. The time-domain analysis has been carried out using LTSpice simulations, including the SPICE model of the bare dies. Cuts on the source copper trace on the module have been made to measure the current flowing in each single die, aiming to validate the model's accuracy. The comparison between the simulation and experimental results shows strong alignment, emphasizing the importance of accurately predicting parasitic elements for current sharing analysis.