In this paper we present DiSR, a first effort for a distributed segment-based approach to routing and defect mapping in a nano-scale, topology agnostic scenario based on DNA self-assembly. The main aim is exploiting the already-proven qualities of segment-based routing without neither requiring a topology graph as input, nor needing a centralized algorithm to configure network paths. After introducing the conceptual elements and the execution model of DiSR, we show how the opensource Nanoxim platform has been used to evaluate the proposed approach in the process of discovering irregular network topology while establishing network segments. Results show how DiSR still preserves some important properties (coverage, defect tolerance, scalability) while avoiding centralized tree-based broadcasting and resource hungry solutions such as virtual channels and hardware redundancy. Finally, we analyzed a first, not yet optimised gate-level hardware implementation of the required control logic and storage for DiSR, demonstrating a relatively acceptable impact ranging from 10 to about 20% of the budget of transistors available for each node.
A first effort for a distributed segment-based approach on self-assembled nano networks
CATANIA, Vincenzo;MONTELEONE, SALVATORE;PATTI, DAVIDE
2013-01-01
Abstract
In this paper we present DiSR, a first effort for a distributed segment-based approach to routing and defect mapping in a nano-scale, topology agnostic scenario based on DNA self-assembly. The main aim is exploiting the already-proven qualities of segment-based routing without neither requiring a topology graph as input, nor needing a centralized algorithm to configure network paths. After introducing the conceptual elements and the execution model of DiSR, we show how the opensource Nanoxim platform has been used to evaluate the proposed approach in the process of discovering irregular network topology while establishing network segments. Results show how DiSR still preserves some important properties (coverage, defect tolerance, scalability) while avoiding centralized tree-based broadcasting and resource hungry solutions such as virtual channels and hardware redundancy. Finally, we analyzed a first, not yet optimised gate-level hardware implementation of the required control logic and storage for DiSR, demonstrating a relatively acceptable impact ranging from 10 to about 20% of the budget of transistors available for each node.File | Dimensione | Formato | |
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