Sfoglia per Autore
Formal VLSI Verification Based on LIPS
file da validare1989-01-01 Carchiolo, Vincenza; Malgeri, Michele Giuseppe
ECCS and LIPS: Two Languages for OSI Systems Specification and Verification
file da validare1989-01-01 Carchiolo, Vincenza; DI STEFANO, Antonella; Faro, A.; Pappalardo, Giuseppe
A Tool for the Performance analysis of Concurrent Systems
file da validare1990-01-01 Carchiolo, Vincenza; Faro, A; Malgeri, M.
On the design of communications systems by ECCS and CSP based approaches
file da validare1990-01-01 Carchiolo, Vincenza; Pappalardo, Giuseppe
Knowledge based approach for parallel software verification
file da validare1990-01-01 Carchiolo, Vincenza; A., Faro
On optimizing test sequence generation
file da validare1990-01-01 Carchiolo, Vincenza; Faro, A.
Case study in protocol verification
file da validare1990-01-01 Carchiolo, Vincenza; DI STEFANO, Antonella; Faro, A.; Pappalardo, G.
A Transputer Architecture for OSI Systems, Transputer
file da validare1991-01-01 Carchiolo, Vincenza; Catania, Vincenzo; Puliafito, A.; Vita, L.
On the design of communication systems by ECCS and CSP based approaches
file da validare1991-01-01 Carchiolo, Vincenza; Pappalardo, Giuseppe
Test sequence generation for VLSI circuit
file da validare1992-01-01 Carchiolo, Vincenza; Malgeri, Michele Giuseppe
Formal Decription techniques and Automated Protocol Synthesis
file da validare1992-01-01 Carchiolo, Vincenza; Faro, A.; Giordano, D.
Formal description techniques and automated protocol synthesis
1992-01-01 Carchiolo, Vincenza; Faro, A; Giordano, Daniela
Using Parallel Programming Language for the performance analysis of concurrent systems
file da validare1993-01-01 Carchiolo, Vincenza; Papale,
Behavioural approach to system codesign
file da validare1993-01-01 Carchiolo, Vincenza; Malgeri, Michele Giuseppe
Using Logic programming in developing parallel deductive database
file da validare1994-01-01 Carchiolo, Vincenza; Malgeri, Michele Giuseppe; M., Papale
The role of simulation in hardware/software codesign
file da validare1994-01-01 Carchiolo, Vincenza; Malgeri, Michele Giuseppe
A formal hardware/software Codesign methodology
file da validare1995-01-01 Carchiolo, Vincenza; Malgeri, Michele Giuseppe
Using CIRCAL for real time system specification
file da validare1995-01-01 Carchiolo, Vincenza; Malgeri, Michele Giuseppe; Mangioni, Giuseppe
A formal approach to step by step codesign methodology
file da validare1995-01-01 Carchiolo, Vincenza; Malgeri, Michele Giuseppe; Mangioni, Giuseppe
Fuzzy approach to co-design system partitioning
file da validare1995-01-01 Carchiolo, Vincenza; Malgeri, Michele Giuseppe
| Titolo | Data di pubblicazione | Autore(i) | File |
|---|---|---|---|
| Formal VLSI Verification Based on LIPS | 1-gen-1989 | Carchiolo, Vincenza; Malgeri, Michele Giuseppe | file da validare |
| ECCS and LIPS: Two Languages for OSI Systems Specification and Verification | 1-gen-1989 | Carchiolo, Vincenza; DI STEFANO, Antonella; Faro, A.; Pappalardo, Giuseppe | file da validare |
| A Tool for the Performance analysis of Concurrent Systems | 1-gen-1990 | Carchiolo, Vincenza; Faro, A; Malgeri, M. | file da validare |
| On the design of communications systems by ECCS and CSP based approaches | 1-gen-1990 | Carchiolo, Vincenza; Pappalardo, Giuseppe | file da validare |
| Knowledge based approach for parallel software verification | 1-gen-1990 | Carchiolo, Vincenza; A., Faro | file da validare |
| On optimizing test sequence generation | 1-gen-1990 | Carchiolo, Vincenza; Faro, A. | file da validare |
| Case study in protocol verification | 1-gen-1990 | Carchiolo, Vincenza; DI STEFANO, Antonella; Faro, A.; Pappalardo, G. | file da validare |
| A Transputer Architecture for OSI Systems, Transputer | 1-gen-1991 | Carchiolo, Vincenza; Catania, Vincenzo; Puliafito, A.; Vita, L. | file da validare |
| On the design of communication systems by ECCS and CSP based approaches | 1-gen-1991 | Carchiolo, Vincenza; Pappalardo, Giuseppe | file da validare |
| Test sequence generation for VLSI circuit | 1-gen-1992 | Carchiolo, Vincenza; Malgeri, Michele Giuseppe | file da validare |
| Formal Decription techniques and Automated Protocol Synthesis | 1-gen-1992 | Carchiolo, Vincenza; Faro, A.; Giordano, D. | file da validare |
| Formal description techniques and automated protocol synthesis | 1-gen-1992 | Carchiolo, Vincenza; Faro, A; Giordano, Daniela | |
| Using Parallel Programming Language for the performance analysis of concurrent systems | 1-gen-1993 | Carchiolo, Vincenza; Papale, | file da validare |
| Behavioural approach to system codesign | 1-gen-1993 | Carchiolo, Vincenza; Malgeri, Michele Giuseppe | file da validare |
| Using Logic programming in developing parallel deductive database | 1-gen-1994 | Carchiolo, Vincenza; Malgeri, Michele Giuseppe; M., Papale | file da validare |
| The role of simulation in hardware/software codesign | 1-gen-1994 | Carchiolo, Vincenza; Malgeri, Michele Giuseppe | file da validare |
| A formal hardware/software Codesign methodology | 1-gen-1995 | Carchiolo, Vincenza; Malgeri, Michele Giuseppe | file da validare |
| Using CIRCAL for real time system specification | 1-gen-1995 | Carchiolo, Vincenza; Malgeri, Michele Giuseppe; Mangioni, Giuseppe | file da validare |
| A formal approach to step by step codesign methodology | 1-gen-1995 | Carchiolo, Vincenza; Malgeri, Michele Giuseppe; Mangioni, Giuseppe | file da validare |
| Fuzzy approach to co-design system partitioning | 1-gen-1995 | Carchiolo, Vincenza; Malgeri, Michele Giuseppe | file da validare |
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