ASCIA, Giuseppe
ASCIA, Giuseppe
INGEGNERIA ELETTRICA ELETTRONICA E INFORMATICA
A closed loop control based power manager for WiNoC architectures
file da validare2014-01-01 Rusli, M. S.; Mineo, A.; Palesi, Maurizio; Ascia, Giuseppe; Catania, Vincenzo; Marsono, M. N.
A closed loop power manager for transmission power control in wireless network-on-chip architectures
2015-01-01 Rusli, M. S.; Mineo, A; Palesi, Maurizio; Ascia, Giuseppe; Catania, Vincenzo; Yee, O. C.; Marsono, M. N.
A closed loop transmitting power self-calibration scheme for energy efficient WiNoC architectures
2015-01-01 Mineo, A; Rusli M., S; Palesi, Maurizio; Ascia, Giuseppe; Catania, Vincenzo; Marsono, M. N.
A Data Dependent Approach to Instruction Level Power Estimation
file da validare1999-01-01 Ascia, Giuseppe; Sarta, D; Trifone, D.
A dedicated parallel processor for fuzzy computation
file da validare1997-01-01 Ascia, Giuseppe; Catania, Vincenzo
A Framework for a Parallel Architecture Dedicated to Soft Computing
file da validare1998-01-01 Ascia, Giuseppe; Catania, Vincenzo
A Framework for Design Space Exploration of Parameterized VLSI Systems
file da validare2002-01-01 Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio
A Fuzzy Buffer Management Scheme for ATM and IP Networks
2001-01-01 Ascia, Giuseppe; Catania, Vincenzo; Panno, Daniela Giovanna Anna
A Fuzzy Buffer management scheme for shared-memory ATM switches
file da validare2000-01-01 Ascia, Giuseppe; Catania, Vincenzo; Lombardo, S; Panno, Daniela Giovanna Anna
A fuzzy system index to preserve interpretability in deep tuning of fuzzy rule based classifiers
2013-01-01 Di Nuovo, A; Ascia, Giuseppe
A GA Based Design Space Exploration Framework for Parameterized System-on-a-Chip Platforms
2004-01-01 Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio
A general purpose processor oriented to fuzzy reasoning
file da validare2001-01-01 Ascia, Giuseppe; Catania, Vincenzo
A genetic approach to bus encoding
file da validare2003-01-01 Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio; Parlato, A.
A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems
file da validare2003-01-01 Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio
A HIGH LEVEL HARDWARE MODEL FOR A PARALLEL FUZZY PROCESSOR
file da validare1994-01-01 Ascia, Giuseppe; Catania, Vincenzo; Puliafito, A.
A High Performance Processor for Application Based on Fuzzy Logic
file da validare1999-01-01 Ascia, Giuseppe; Catania, Vincenzo
A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip
2006-01-01 Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio
A Multiobjective Genetic Fuzzy Approach for Intelligent System-level Exploration in Parameterized VLIW Processor Design
file da validare2006-01-01 Ascia, Giuseppe; Catania, Vincenzo; DI NUOVO A., G; Palesi, Maurizio; Patti, Davide
A New Selection Policy for Adaptive Routing in Network on Chip
file da validare2006-01-01 Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio; Patti, Davide
A Novel Approach to Design Space Exploration of Parameterized SOCs
file da validare2001-01-01 Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio
| Titolo | Data di pubblicazione | Autore(i) | File |
|---|---|---|---|
| A closed loop control based power manager for WiNoC architectures | 1-gen-2014 | Rusli, M. S.; Mineo, A.; Palesi, Maurizio; Ascia, Giuseppe; Catania, Vincenzo; Marsono, M. N. | file da validare |
| A closed loop power manager for transmission power control in wireless network-on-chip architectures | 1-gen-2015 | Rusli, M. S.; Mineo, A; Palesi, Maurizio; Ascia, Giuseppe; Catania, Vincenzo; Yee, O. C.; Marsono, M. N. | |
| A closed loop transmitting power self-calibration scheme for energy efficient WiNoC architectures | 1-gen-2015 | Mineo, A; Rusli M., S; Palesi, Maurizio; Ascia, Giuseppe; Catania, Vincenzo; Marsono, M. N. | |
| A Data Dependent Approach to Instruction Level Power Estimation | 1-gen-1999 | Ascia, Giuseppe; Sarta, D; Trifone, D. | file da validare |
| A dedicated parallel processor for fuzzy computation | 1-gen-1997 | Ascia, Giuseppe; Catania, Vincenzo | file da validare |
| A Framework for a Parallel Architecture Dedicated to Soft Computing | 1-gen-1998 | Ascia, Giuseppe; Catania, Vincenzo | file da validare |
| A Framework for Design Space Exploration of Parameterized VLSI Systems | 1-gen-2002 | Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio | file da validare |
| A Fuzzy Buffer Management Scheme for ATM and IP Networks | 1-gen-2001 | Ascia, Giuseppe; Catania, Vincenzo; Panno, Daniela Giovanna Anna | |
| A Fuzzy Buffer management scheme for shared-memory ATM switches | 1-gen-2000 | Ascia, Giuseppe; Catania, Vincenzo; Lombardo, S; Panno, Daniela Giovanna Anna | file da validare |
| A fuzzy system index to preserve interpretability in deep tuning of fuzzy rule based classifiers | 1-gen-2013 | Di Nuovo, A; Ascia, Giuseppe | |
| A GA Based Design Space Exploration Framework for Parameterized System-on-a-Chip Platforms | 1-gen-2004 | Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio | |
| A general purpose processor oriented to fuzzy reasoning | 1-gen-2001 | Ascia, Giuseppe; Catania, Vincenzo | file da validare |
| A genetic approach to bus encoding | 1-gen-2003 | Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio; Parlato, A. | file da validare |
| A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems | 1-gen-2003 | Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio | file da validare |
| A HIGH LEVEL HARDWARE MODEL FOR A PARALLEL FUZZY PROCESSOR | 1-gen-1994 | Ascia, Giuseppe; Catania, Vincenzo; Puliafito, A. | file da validare |
| A High Performance Processor for Application Based on Fuzzy Logic | 1-gen-1999 | Ascia, Giuseppe; Catania, Vincenzo | file da validare |
| A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip | 1-gen-2006 | Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio | |
| A Multiobjective Genetic Fuzzy Approach for Intelligent System-level Exploration in Parameterized VLIW Processor Design | 1-gen-2006 | Ascia, Giuseppe; Catania, Vincenzo; DI NUOVO A., G; Palesi, Maurizio; Patti, Davide | file da validare |
| A New Selection Policy for Adaptive Routing in Network on Chip | 1-gen-2006 | Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio; Patti, Davide | file da validare |
| A Novel Approach to Design Space Exploration of Parameterized SOCs | 1-gen-2001 | Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio | file da validare |