ASCIA, Giuseppe

ASCIA, Giuseppe  

INGEGNERIA ELETTRICA ELETTRONICA E INFORMATICA  

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Titolo Data di pubblicazione Autore(i) File
A closed loop control based power manager for WiNoC architectures 1-gen-2014 Rusli, M. S.; Mineo, A.; Palesi, Maurizio; Ascia, Giuseppe; Catania, Vincenzo; Marsono, M. N.
A Data Dependent Approach to Instruction Level Power Estimation 1-gen-1999 Ascia, Giuseppe; Sarta, D; Trifone, D.
A dedicated parallel processor for fuzzy computation 1-gen-1997 Ascia, Giuseppe; Catania, Vincenzo
A Framework for Design Space Exploration of Parameterized VLSI Systems 1-gen-2002 Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio
A Fuzzy Buffer Management Scheme for ATM and IP Networks 1-gen-2001 Ascia, Giuseppe; Catania, Vincenzo; Panno, Daniela Giovanna Anna
A Fuzzy Buffer management scheme for shared-memory ATM switches 1-gen-2000 Ascia, Giuseppe; Catania, Vincenzo; Lombardo, S; Panno, Daniela Giovanna Anna
A fuzzy system index to preserve interpretability in deep tuning of fuzzy rule based classifiers 1-gen-2013 Di Nuovo, A; Ascia, Giuseppe
A GA Based Design Space Exploration Framework for Parameterized System-on-a-Chip Platforms 1-gen-2004 Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio
A general purpose processor oriented to fuzzy reasoning 1-gen-2001 Ascia, Giuseppe; Catania, Vincenzo
A genetic approach to bus encoding 1-gen-2003 Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio; Parlato, A.
A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems 1-gen-2003 Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio
A HIGH LEVEL HARDWARE MODEL FOR A PARALLEL FUZZY PROCESSOR 1-gen-1994 Ascia, Giuseppe; Catania, Vincenzo; Puliafito, A.
A High Performance Processor for Application Based on Fuzzy Logic 1-gen-1999 Ascia, Giuseppe; Catania, Vincenzo
A New Selection Policy for Adaptive Routing in Network on Chip 1-gen-2006 Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio; Patti, Davide
A Novel Approach to Design Space Exploration of Parameterized SOCs 1-gen-2001 Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio
A Parallel Processor Architecture for Real-Time Fuzzy Applications 1-gen-1998 Ascia, Giuseppe; Catania, Vincenzo
A pipeline parallel architecture for a fuzzy inference processor 1-gen-2000 Ascia, Giuseppe; Catania, Vincenzo
A reconfigurable parallel architecture for a fuzzy processor 1-gen-1994 Ascia, Giuseppe; Catania, Vincenzo; Puliafito, A; Vita, L.
A reconfigurable parallel architecture for a fuzzy processor 1-gen-1996 Ascia, Giuseppe; Catania, Vincenzo; Puliafito, A; Vita, L.
A Soft Computing Technique for Performance Enhancement in High Speed Shared-Memory Switches 1-gen-2000 Ascia, Giuseppe; Catania, Vincenzo; Panno, Daniela Giovanna Anna