Advances in technology now make it possible to integrate hundreds of cores (e.g. generalor special purpose processors, embedded memories, application specific components, mixedsignalI/O cores) in a single silicon die. The large number of resources that have to communicatemakes the use of interconnection systems based on shared buses inefficient. One way to solve theproblem of on-chip communications is to use a Network-on-Chip (NoC)-based communicationinfrastructure. Such interconnection systems offer new degrees of freedom, exploration of whichmay reveal significant optimization possibilities: the possibility of arranging the computing andstorage resources in an NoC, for example, has a great impact on various performance indexes.The paper addresses the problem of topological mapping of intellectual properties (IPs) on thetiles of a mesh-based NoC architecture. The aim is to obtain the Pareto mappings that maximizeperformance and minimize power dissipation. We propose a heuristic technique based on evolutionarycomputing to obtain an optimal approximation of the Pareto-optimal front in an efficientand accurate way. At the same time, two of the most widely-known approaches to mapping inmesh-based NoC architectures are extended in order to explore the mapping space in a multicriteriamode. The approaches are then evaluated and compared, in terms of both accuracy andefficiency, on a platform based on an event-driven trace-based simulator which makes it possibleto take account of important dynamic effects that have a great impact on mapping. The evaluationperformed on both synthesized traffic and real applications (an MPEG-4 codec) confirms theefficiency, accuracy and scalability of the proposed approach.
|Titolo:||A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip|
|Data di pubblicazione:||2006|
|Appare nelle tipologie:||1.1 Articolo in rivista|