PALESI, MAURIZIO
PALESI, MAURIZIO
INGEGNERIA ELETTRICA ELETTRONICA E INFORMATICA
A closed loop control based power manager for WiNoC architectures
2014-01-01 Rusli, M. S.; Mineo, A.; Palesi, Maurizio; Ascia, Giuseppe; Catania, Vincenzo; Marsono, M. N.
A Communication-Aware Topological Mapping Technique for NoCs
2008-01-01 Tornero, R; ORDUNA J., M; Palesi, Maurizio; Duato, J.
A Framework for Design Space Exploration of Parameterized VLSI Systems
2002-01-01 Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio
A GA Based Design Space Exploration Framework for Parameterized System-on-a-Chip Platforms
2004-01-01 Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio
A genetic approach to bus encoding
2003-01-01 Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio; Parlato, A.
A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems
2003-01-01 Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio
A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures
2006-01-01 Palesi, Maurizio; Kumar, S; Holsmark, R.
A Methodology for Design of Application Specific Deadlock-free Routing Algorithms for NoC Systems
2006-01-01 Palesi, Maurizio; Holsmark, R; Kumar, S; Catania, Vincenzo
A Multi-Level Routing Scheme and Router Architecture to support Hierarchical Routing in Large Network on Chip Platforms
2010-01-01 R., Holsmark; S., Kumar; Palesi, Maurizio
A Multi-objective Strategy for Concurrent Mapping and Routing in Networks on Chip
2009-01-01 Tornero, R; Sterrantino, V; Palesi, Maurizio; Orduna, J. M.
A New Selection Policy for Adaptive Routing in Network on Chip
2006-01-01 Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio; Patti, Davide
A Novel Approach to Design Space Exploration of Parameterized SOCs
2001-01-01 Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio
A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems
2005-01-01 Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio; Patti, Davide
ACDC: An Accuracy- and Congestion-aware Dynamic Traffic Control Method for Networks-on-Chip
2019-01-01 Xiao, S.; Wang, X.; Palesi, M.; Singh, A. K.; Mak, T.
An adaptive output selection function based on a fuzzy rule base system for Network on Chip
2013-01-01 Ascia, Giuseppe; Palesi, Maurizio; Catania, Vincenzo
Adaptive Packet Relocator in Wireless Network-on-Chip (WiNoC)
2017-01-01 Shahrizal Rusli, Mohd; Lit, Asrani; Nadzir Marsono, Muhammad; Palesi, Maurizio
Adaptive Power Allocation for Many-core Systems Inspired from A Multi-agent Auction Model
2014-01-01 X. Wang, X.; Zhao, B.; Mak, T.; Yang, M.; Jiang, Y.; Daneshtalab, M.; Palesi, Maurizio
An Adaptive Routing Technique Supporting In-Order Packet Delivery in Networks on Chip
2010-01-01 Palesi, Maurizio; Holsmark, R; Wang, X; Kumar, S; Yang, M; Jiang, Y; Catania, Vincenzo
An Adaptive Transmitting Power Technique for Energy Efficient mm-Wave Wireless NoCs
2014-01-01 Mineo, A; Palesi, Maurizio; Ascia, Giuseppe; Catania, Vincenzo
An Effective Methodology to Multi-objective Design of Application Domain-specific Embedded architectures
2009-01-01 Catania, Vincenzo; DE FRANCISCI MORALES, G; DI NUOVO A., G; Palesi, Maurizio; Patti, Davide