PALESI, MAURIZIO

PALESI, MAURIZIO  

INGEGNERIA ELETTRICA ELETTRONICA E INFORMATICA  

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Risultati 1 - 20 di 174 (tempo di esecuzione: 0.063 secondi).
Titolo Data di pubblicazione Autore(i) File
A closed loop control based power manager for WiNoC architectures 1-gen-2014 Rusli, M. S.; Mineo, A.; Palesi, Maurizio; Ascia, Giuseppe; Catania, Vincenzo; Marsono, M. N.
A Communication-Aware Topological Mapping Technique for NoCs 1-gen-2008 Tornero, R; ORDUNA J., M; Palesi, Maurizio; Duato, J.
A Framework for Design Space Exploration of Parameterized VLSI Systems 1-gen-2002 Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio
A GA Based Design Space Exploration Framework for Parameterized System-on-a-Chip Platforms 1-gen-2004 Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio
A genetic approach to bus encoding 1-gen-2003 Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio; Parlato, A.
A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems 1-gen-2003 Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio
A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures 1-gen-2006 Palesi, Maurizio; Kumar, S; Holsmark, R.
A Methodology for Design of Application Specific Deadlock-free Routing Algorithms for NoC Systems 1-gen-2006 Palesi, Maurizio; Holsmark, R; Kumar, S; Catania, Vincenzo
A Multi-Level Routing Scheme and Router Architecture to support Hierarchical Routing in Large Network on Chip Platforms 1-gen-2010 R., Holsmark; S., Kumar; Palesi, Maurizio
A Multi-objective Strategy for Concurrent Mapping and Routing in Networks on Chip 1-gen-2009 Tornero, R; Sterrantino, V; Palesi, Maurizio; Orduna, J. M.
A New Selection Policy for Adaptive Routing in Network on Chip 1-gen-2006 Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio; Patti, Davide
A Novel Approach to Design Space Exploration of Parameterized SOCs 1-gen-2001 Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio
A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems 1-gen-2005 Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio; Patti, Davide
ACDC: An Accuracy- and Congestion-aware Dynamic Traffic Control Method for Networks-on-Chip 1-gen-2019 Xiao, S.; Wang, X.; Palesi, M.; Singh, A. K.; Mak, T.
An adaptive output selection function based on a fuzzy rule base system for Network on Chip 1-gen-2013 Ascia, Giuseppe; Palesi, Maurizio; Catania, Vincenzo
Adaptive Packet Relocator in Wireless Network-on-Chip (WiNoC) 1-gen-2017 Shahrizal Rusli, Mohd; Lit, Asrani; Nadzir Marsono, Muhammad; Palesi, Maurizio
Adaptive Power Allocation for Many-core Systems Inspired from A Multi-agent Auction Model 1-gen-2014 X. Wang, X.; Zhao, B.; Mak, T.; Yang, M.; Jiang, Y.; Daneshtalab, M.; Palesi, Maurizio
An Adaptive Routing Technique Supporting In-Order Packet Delivery in Networks on Chip 1-gen-2010 Palesi, Maurizio; Holsmark, R; Wang, X; Kumar, S; Yang, M; Jiang, Y; Catania, Vincenzo
An Adaptive Transmitting Power Technique for Energy Efficient mm-Wave Wireless NoCs 1-gen-2014 Mineo, A; Palesi, Maurizio; Ascia, Giuseppe; Catania, Vincenzo
An Effective Methodology to Multi-objective Design of Application Domain-specific Embedded architectures 1-gen-2009 Catania, Vincenzo; DE FRANCISCI MORALES, G; DI NUOVO A., G; Palesi, Maurizio; Patti, Davide