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PALESI, MAURIZIO

PALESI, MAURIZIO  

INGEGNERIA ELETTRICA ELETTRONICA E INFORMATICA  

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Risultati 1 - 20 di 199 (tempo di esecuzione: 0.049 secondi).
Titolo Data di pubblicazione Autore(i) File
A Characteristics-Based Least Common Multiple Algorithm to Optimize Magnetic-Field-Based Indoor Localization 1-gen-2025 Rafique, Hamaad; Patti, Davide; Palesi, Maurizio; La Delfa, Gaetano Carmelo file da validare
A closed loop control based power manager for WiNoC architectures 1-gen-2014 Rusli, M. S.; Mineo, A.; Palesi, Maurizio; Ascia, Giuseppe; Catania, Vincenzo; Marsono, M. N. file da validare
A closed loop power manager for transmission power control in wireless network-on-chip architectures 1-gen-2015 Rusli, M. S.; Mineo, A; Palesi, Maurizio; Ascia, Giuseppe; Catania, Vincenzo; Yee, O. C.; Marsono, M. N.
A closed loop transmitting power self-calibration scheme for energy efficient WiNoC architectures 1-gen-2015 Mineo, A; Rusli M., S; Palesi, Maurizio; Ascia, Giuseppe; Catania, Vincenzo; Marsono, M. N.
A Communication-Aware Topological Mapping Technique for NoCs 1-gen-2008 Tornero, R; ORDUNA J., M; Palesi, Maurizio; Duato, J. file da validare
A Data-Driven Approach to Dataflow-Aware Online Scheduling for Graph Neural Network Inference 1-gen-2025 Puigdemont, Pol; Russo, Enrico; Wassington, Axel; Das, Abhijit; Abadal, Sergi; Palesi, Maurizio file da validare
A Deep Reinforcement Learning based Online Scheduling Policy for Deep Neural Network Multi-Tenant Multi-Accelerator Systems 1-gen-2024 Blanco, Francesco Giulio; Russo, Enrico; Palesi, Maurizio; Patti, Davide; Ascia, Giuseppe; Catania, Vincenzo
A Framework for Design Space Exploration of Parameterized VLSI Systems 1-gen-2002 Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio file da validare
A GA Based Design Space Exploration Framework for Parameterized System-on-a-Chip Platforms 1-gen-2004 Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio
A genetic approach to bus encoding 1-gen-2003 Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio; Parlato, A. file da validare
A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems 1-gen-2003 Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio file da validare
A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures 1-gen-2006 Palesi, Maurizio; Kumar, S; Holsmark, R. file da validare
A Methodology for Design of Application Specific Deadlock-free Routing Algorithms for NoC Systems 1-gen-2006 Palesi, Maurizio; Holsmark, R; Kumar, S; Catania, Vincenzo file da validare
A Methodology for Simulating Multi-chiplet Systems Using Open-source Simulators 1-gen-2021 Zhi, Hc; Xu, Xn; Han, Wj; Gao, Zl; Wang, Xh; Palesi, M; Singh, Ak; Huang, Lt
A Multi-Level Routing Scheme and Router Architecture to support Hierarchical Routing in Large Network on Chip Platforms 1-gen-2010 R., Holsmark; S., Kumar; Palesi, Maurizio file da validare
A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip 1-gen-2006 Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio
A Multi-objective Strategy for Concurrent Mapping and Routing in Networks on Chip 1-gen-2009 Tornero, R; Sterrantino, V; Palesi, Maurizio; Orduna, J. M. file da validare
A Multiobjective Genetic Fuzzy Approach for Intelligent System-level Exploration in Parameterized VLIW Processor Design 1-gen-2006 Ascia, Giuseppe; Catania, Vincenzo; DI NUOVO A., G; Palesi, Maurizio; Patti, Davide file da validare
A New Selection Policy for Adaptive Routing in Network on Chip 1-gen-2006 Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio; Patti, Davide file da validare
A Novel Approach to Design Space Exploration of Parameterized SOCs 1-gen-2001 Ascia, Giuseppe; Catania, Vincenzo; Palesi, Maurizio file da validare