In a wireless Network-on-Chip (WiNoC) the radio transceiver accounts for a significant fraction of the total communication energy. Recently, a configurable transceiver architecture able to regulate its transmitting power based on the location of the destination node has been proposed. Unfortunately, the use of such transceiver requires a costly, time consuming and complex characterization phase performed at design time and mainly based on the use of field solver simulators whose accuracy has not yet been proved in the context of integrated on-chip antennas. In this paper we present a closed loop transmitting power self-calibration mechanism which allows to determine on-line the optimal transmitting power for each transmitting and receiving pair in a WiNoC. The proposed mechanism is general and can be applied to any WiNoC architecture with a low overhead in terms of silicon area. Its application to three well known WiNoC architectures shows its effectiveness in drastically reducing the overall communication energy (up to 50%) with a limited impact on performance.

A closed loop transmitting power self-calibration scheme for energy efficient WiNoC architectures

PALESI, MAURIZIO;ASCIA, Giuseppe;CATANIA, Vincenzo;
2015-01-01

Abstract

In a wireless Network-on-Chip (WiNoC) the radio transceiver accounts for a significant fraction of the total communication energy. Recently, a configurable transceiver architecture able to regulate its transmitting power based on the location of the destination node has been proposed. Unfortunately, the use of such transceiver requires a costly, time consuming and complex characterization phase performed at design time and mainly based on the use of field solver simulators whose accuracy has not yet been proved in the context of integrated on-chip antennas. In this paper we present a closed loop transmitting power self-calibration mechanism which allows to determine on-line the optimal transmitting power for each transmitting and receiving pair in a WiNoC. The proposed mechanism is general and can be applied to any WiNoC architecture with a low overhead in terms of silicon area. Its application to three well known WiNoC architectures shows its effectiveness in drastically reducing the overall communication energy (up to 50%) with a limited impact on performance.
2015
978-3-9815-3704-8
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.11769/73198
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