| Nome |
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Analysis and Comparison in the Energy-Delay Space of Nanometer CMOS One-Bit Full-Adders, file 45169b8d-f7e4-4062-bdd9-c2e762b017e6
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12
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Design of Three-Stage OTA Based on Settling-Time Requirements Including Large and Small Signal Behavior, file dfe4d22e-25d0-bb0a-e053-d805fe0a78d9
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12
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Compensation strategy for high-speed three-stage switched-capacitor amplifiers, file dfe4d227-300b-bb0a-e053-d805fe0a78d9
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10
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A 50-mA 1-nF Low-Voltage Low-Dropout Voltage Regulator for SoC Applications, file dfe4d227-d4b5-bb0a-e053-d805fe0a78d9
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10
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A gm/ID-Based Design Strategy for IoT and Ultra-Low-Power OTAs with Fast-Settling and Large Capacitive Loads, file dfe4d22e-9b2c-bb0a-e053-d805fe0a78d9
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10
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A Biasing Approach to design Ultra-Low-Power Standard-Cell-Based Analog Building Blocks for Nanometer SoCs, file dfe4d22e-c9e5-bb0a-e053-d805fe0a78d9
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10
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Efficient design strategy for optimizing the settling time in three-stage amplifiers including small-and large-signal behavior, file dfe4d22e-af33-bb0a-e053-d805fe0a78d9
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9
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A Novel Clock Gating Approach for the Design of Low-Power Linear Feedback Shift Registers, file aa10a3b7-7cd6-4dd6-8111-b1c7d31f7e95
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7
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Theoretical and experimental study of the role of cell-cell dipole interaction in dielectrophoretic devices: application to polynomial electrodes, file dfe4d227-1c75-bb0a-e053-d805fe0a78d9
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7
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Behavioral model of silicon photo-multipliers suitable for transistor-level circuit simulation, file dfe4d22e-d9b6-bb0a-e053-d805fe0a78d9
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7
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Fractional Order Differ-Integral Operator in Integrated Technology, file dfe4d227-54bb-bb0a-e053-d805fe0a78d9
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5
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Robust design of CMOS amplifiers oriented to settling-time specification, file dfe4d228-6015-bb0a-e053-d805fe0a78d9
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5
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1V CMOS output stage with excellent linearity, file dfe4d227-095c-bb0a-e053-d805fe0a78d9
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3
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Design Methodology of the Output Power Stage of a Step-Down DC-DC Converter, file 2fed0c5e-1d0c-4dfc-be1f-9917b7abbd13
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2
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Dynamic-biased capacitor-free NMOS LDO voltage regulator, file dfe4d227-0957-bb0a-e053-d805fe0a78d9
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2
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Analysis and optimization of a novel CMOS multiplier, file dfe4d227-095d-bb0a-e053-d805fe0a78d9
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2
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CMRR frequency response of CMOS operational transconductance amplifiers, file dfe4d227-095e-bb0a-e053-d805fe0a78d9
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2
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A novel 1-V class-AB transconductor for improving speed performance in SC applications, file dfe4d227-619f-bb0a-e053-d805fe0a78d9
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2
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Integrated Quenching-and-Reset Circuit for Single-Photon Avalanche Diodes, file dfe4d227-d4c5-bb0a-e053-d805fe0a78d9
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2
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LDO Compensation Strategy based on Current Buffer/Amplifiers, file dfe4d227-d606-bb0a-e053-d805fe0a78d9
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2
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Two-Stage OTA Design Based on Settling-Time Constraints, file dfe4d227-dab8-bb0a-e053-d805fe0a78d9
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2
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A new method for evaluating harmonic distortion in push-pull output stages, file dfe4d227-db2a-bb0a-e053-d805fe0a78d9
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2
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Harmonic distortion in single-stage amplifiers, file dfe4d227-db56-bb0a-e053-d805fe0a78d9
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2
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Analysis of Power Supply Gain of CMOS Bandgap References, file dfe4d227-e101-bb0a-e053-d805fe0a78d9
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2
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In-Depth Analysis of Pole-Zero Compensations in CMOS Operational Transconductance Amplifiers, file dfe4d229-e90f-bb0a-e053-d805fe0a78d9
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2
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Class-AB CMOS output stages suitable for low-voltage amplifiers in nanometer technologies, file dfe4d229-eb5d-bb0a-e053-d805fe0a78d9
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2
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Resistance of Feedback Amplifiers: A Novel Representation, file dfe4d226-f6d7-bb0a-e053-d805fe0a78d9
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1
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On-chip low drop-out voltage regulator with NMOS power transistor and dynamic biasing technique, file dfe4d227-0958-bb0a-e053-d805fe0a78d9
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1
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Exploiting the High-Frequency Performance of Low-Voltage Low-Power SC Filters, file dfe4d227-0959-bb0a-e053-d805fe0a78d9
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1
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Analysis, modelling and optimization of a gain boosted telescopic amplifier, file dfe4d227-095a-bb0a-e053-d805fe0a78d9
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1
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A Low-Voltage Low-Power Voltage Reference Based on Subthreshold MOSFETs, file dfe4d227-095b-bb0a-e053-d805fe0a78d9
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1
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1.5V power supply CMOS voltage squarer, file dfe4d227-095f-bb0a-e053-d805fe0a78d9
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1
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An Accurate Ultra-Compact I–V Model for Nanometer MOS Transistors With Applications on Digital Circuits, file dfe4d227-09d6-bb0a-e053-d805fe0a78d9
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1
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Statistical modelling and design guidelines of CMOS current references, file dfe4d227-11c5-bb0a-e053-d805fe0a78d9
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1
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An approach to test the open-loop parameters of feedback amplifiers, file dfe4d227-122a-bb0a-e053-d805fe0a78d9
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1
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Robust Miller Compensation With Current Amplifiers Applied to LDO Voltage Regulator, file dfe4d227-3301-bb0a-e053-d805fe0a78d9
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1
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Three-Stage Dynamic-Biased CMOS Amplifier With a Robust Optimization of the Settling Time, file dfe4d227-3dd8-bb0a-e053-d805fe0a78d9
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1
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Study of the role of particle-particle dipole interaction in dielectrophoretic devices for biomarkers identification, file dfe4d227-4c02-bb0a-e053-d805fe0a78d9
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1
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A simple extraction procedure for determining the electrical parameters in Silicon Photomultipliers, file dfe4d227-5b1f-bb0a-e053-d805fe0a78d9
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1
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Analysis and optimization of gain-boosted telescopic amplifiers, file dfe4d227-5c54-bb0a-e053-d805fe0a78d9
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1
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Verilog-a modeling of Silicon Photo-Multipliers, file dfe4d227-6482-bb0a-e053-d805fe0a78d9
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1
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1.2-V CMOS op-amp with a dynamically biased output stage, file dfe4d227-d3de-bb0a-e053-d805fe0a78d9
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1
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Current-mode A/D fuzzy converter, file dfe4d227-d3df-bb0a-e053-d805fe0a78d9
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1
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A Detailed Analysis of Power-Supply Noise Attenuation in Bandgap Voltage References, file dfe4d227-d425-bb0a-e053-d805fe0a78d9
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1
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Design and Comparison of Very Low-Voltage CMOS Output Stages, file dfe4d227-d4dd-bb0a-e053-d805fe0a78d9
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1
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Behavioral modeling of statistical phenomena of single-photon avalanche diodes, file dfe4d227-d4ea-bb0a-e053-d805fe0a78d9
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1
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High-Drive and Linear CMOS Class-AB Pseudo-Differential Amplifier, file dfe4d227-d50e-bb0a-e053-d805fe0a78d9
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1
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A switched-capacitor compatible membership function block, file dfe4d227-d545-bb0a-e053-d805fe0a78d9
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1
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Low-voltage LDO Compensation Strategy based on Current Amplifiers, file dfe4d227-d5ce-bb0a-e053-d805fe0a78d9
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1
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Sample frequency effects on a new SC realization of Fractional Order Integrator, file dfe4d227-d63d-bb0a-e053-d805fe0a78d9
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1
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Analysis of power supply noise attenuation in a PTAT current source, file dfe4d227-d64e-bb0a-e053-d805fe0a78d9
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1
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A 1-V CMOS Output Stage with High Linearity, file dfe4d227-d67f-bb0a-e053-d805fe0a78d9
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1
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Verilog-a Modeling of SPAD Statistical Phenomena, file dfe4d227-d701-bb0a-e053-d805fe0a78d9
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1
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Logic Gates Dynamic Modeling by Means of an Ultra-Compact MOS Model, file dfe4d227-d736-bb0a-e053-d805fe0a78d9
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1
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An ultra-compact MOS model in nanometer technologies, file dfe4d227-d737-bb0a-e053-d805fe0a78d9
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1
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Monolithic Quenching-and-Reset Circuit for Single-Photon Avalanche Diodes, file dfe4d227-d76f-bb0a-e053-d805fe0a78d9
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1
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Statistical Analysis of CMOS Current Reference, file dfe4d227-d77a-bb0a-e053-d805fe0a78d9
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1
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Switched capacitor compatible minimum-maximum function, file dfe4d227-d7dd-bb0a-e053-d805fe0a78d9
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1
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An efficient fuzzy controller architecture in SC technique, file dfe4d227-d7e1-bb0a-e053-d805fe0a78d9
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1
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A New Method for Harmonic Distortion Analysis in Class-AB Stages, file dfe4d227-d7e7-bb0a-e053-d805fe0a78d9
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1
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CMOS implementation of an extended CNN cell to deal with complex dynamics, file dfe4d227-d997-bb0a-e053-d805fe0a78d9
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1
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Design of low-voltage low-power SC filters for high-frequency applications, file dfe4d227-da20-bb0a-e053-d805fe0a78d9
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1
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Sigma-Delta A/D Fuzzy Converter, file dfe4d227-dac3-bb0a-e053-d805fe0a78d9
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1
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High-linear class AB transconductor for high-frequency applications, file dfe4d227-db2d-bb0a-e053-d805fe0a78d9
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1
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Statistical analysis of the resolution in a current-mode ADC, file dfe4d227-dba1-bb0a-e053-d805fe0a78d9
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1
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Approach to the design of low-voltage SC filters, file dfe4d227-dc0e-bb0a-e053-d805fe0a78d9
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1
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Techniques for evaluating harmonic distortion in class-AB output stages: A tutorial, file dfe4d227-dc0f-bb0a-e053-d805fe0a78d9
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1
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Design guidelines of CMOS class-AB output stages: a tutorial, file dfe4d227-dd3c-bb0a-e053-d805fe0a78d9
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1
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Resolution of a Current-Mode Algorithmic Analog-to-Digital Converter, file dfe4d227-dd6e-bb0a-e053-d805fe0a78d9
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1
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Comparison of Methods for Predicting Distortion in Class-AB Stages, file dfe4d227-df00-bb0a-e053-d805fe0a78d9
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1
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A new voltage reference topology based on subthreshold MOSFETs, file dfe4d227-df71-bb0a-e053-d805fe0a78d9
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1
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Guidelines for Designing Class-AB Output Stages, file dfe4d227-dfa4-bb0a-e053-d805fe0a78d9
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1
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Rosenstark-like Representation of Feedback Amplifier Resistance, file dfe4d227-e01e-bb0a-e053-d805fe0a78d9
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1
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Modeling of EMI propagation in switched-capacitor ΣΔ A/D converter, file dfe4d227-e09b-bb0a-e053-d805fe0a78d9
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1
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NMOS Low Drop-Out Regulator with Dynamic Biasing, file dfe4d227-e09c-bb0a-e053-d805fe0a78d9
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1
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Theoretical and experimental study of the kinetics of particle chains near electrodes in dielectrophoretic devices, file dfe4d227-e0da-bb0a-e053-d805fe0a78d9
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1
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Inverter transfer curves and SRAM noise margin evaluation based on an ultra-compact MOS model, file dfe4d227-e0db-bb0a-e053-d805fe0a78d9
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1
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Analysis and Optimization of a Low-Voltage Class-AB Output Stage, file dfe4d227-e152-bb0a-e053-d805fe0a78d9
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1
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High Linear Bipolar Voltage to Current Converter, file dfe4d227-e774-bb0a-e053-d805fe0a78d9
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1
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HIGH–DRIVE CMOS CURRENT–FEEDBACK OPAMP, file dfe4d227-ef7f-bb0a-e053-d805fe0a78d9
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1
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Bessel-like compensation of three-stage operational transconductance amplifiers, file dfe4d229-1115-bb0a-e053-d805fe0a78d9
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1
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A Clock Boosted Charge Pump with Reduced Rise Time, file dfe4d229-995c-bb0a-e053-d805fe0a78d9
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1
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High-dimensional dynamics in a single-transistor oscillator containing Feynman-Sierpiński resonators: Effect of fractal depth and irregularity, file dfe4d229-997a-bb0a-e053-d805fe0a78d9
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1
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Autonomous Energy-Efficient Wireless Sensor Network Platform for Home/Office Automation, file dfe4d229-9ed6-bb0a-e053-d805fe0a78d9
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1
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Optimized Charge Pump with Clock Booster for Reduced Rise Time or Silicon Area, file dfe4d229-e911-bb0a-e053-d805fe0a78d9
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1
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Design of CMOS OTAs with Settling-Time Constraints, file dfe4d229-e96f-bb0a-e053-d805fe0a78d9
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1
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Settling-time oriented OTA design through the approximation of the ideal delay, file dfe4d22d-0f36-bb0a-e053-d805fe0a78d9
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1
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Non-Inverting Class-AB CMOS Output Stage for Driving High-Capacitive Loads, file dfe4d22d-542d-bb0a-e053-d805fe0a78d9
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1
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Design of CMOS three-stage amplifiers for near-to-minimum settling-time, file dfe4d22e-25cf-bb0a-e053-d805fe0a78d9
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1
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Design of three-stage OTAs from settling-time and slew-rate constraints, file dfe4d22e-d9b8-bb0a-e053-d805fe0a78d9
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1
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Hybrid Full Adders: Optimized Design, Critical Review and Comparison in the Energy-Delay Space, file e77093e5-4d5d-4d03-bdb3-fb133bc9f613
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1
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| Totale |
198 |