IRIS
GIUSTOLISI, Gianluca
 Distribuzione geografica
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Continente #
NA - Nord America 4.988
AS - Asia 2.861
EU - Europa 2.790
SA - Sud America 502
AF - Africa 411
OC - Oceania 31
Continente sconosciuto - Info sul continente non disponibili 7
AN - Antartide 1
Totale 11.591
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Nazione #
US - Stati Uniti d'America 4.798
SG - Singapore 1.381
CN - Cina 782
RU - Federazione Russa 704
IT - Italia 703
IE - Irlanda 416
BR - Brasile 406
UA - Ucraina 294
VN - Vietnam 270
CI - Costa d'Avorio 238
FR - Francia 164
CA - Canada 154
NL - Olanda 144
KR - Corea 94
DE - Germania 76
IN - India 75
GB - Regno Unito 70
NG - Nigeria 57
FI - Finlandia 55
SN - Senegal 53
HK - Hong Kong 51
SE - Svezia 40
AR - Argentina 38
BD - Bangladesh 32
CH - Svizzera 25
JP - Giappone 24
TW - Taiwan 24
MX - Messico 20
CZ - Repubblica Ceca 18
AU - Australia 17
IQ - Iraq 17
AT - Austria 15
PK - Pakistan 15
PL - Polonia 15
NZ - Nuova Zelanda 14
EG - Egitto 13
TR - Turchia 13
EC - Ecuador 12
UZ - Uzbekistan 11
BJ - Benin 10
ES - Italia 10
VE - Venezuela 10
ID - Indonesia 9
PE - Perù 9
ZA - Sudafrica 9
CL - Cile 7
CO - Colombia 7
JO - Giordania 7
PH - Filippine 7
PY - Paraguay 7
DZ - Algeria 6
EU - Europa 6
KE - Kenya 6
MA - Marocco 6
SA - Arabia Saudita 6
TN - Tunisia 6
ET - Etiopia 5
GR - Grecia 5
NP - Nepal 5
AE - Emirati Arabi Uniti 4
BY - Bielorussia 4
IL - Israele 4
JM - Giamaica 4
LB - Libano 4
MY - Malesia 4
TH - Thailandia 4
AZ - Azerbaigian 3
BO - Bolivia 3
KZ - Kazakistan 3
LT - Lituania 3
NO - Norvegia 3
RO - Romania 3
BG - Bulgaria 2
CR - Costa Rica 2
DK - Danimarca 2
EE - Estonia 2
GA - Gabon 2
HN - Honduras 2
HR - Croazia 2
HU - Ungheria 2
IR - Iran 2
KG - Kirghizistan 2
MD - Moldavia 2
MT - Malta 2
NI - Nicaragua 2
OM - Oman 2
RS - Serbia 2
TT - Trinidad e Tobago 2
UY - Uruguay 2
AL - Albania 1
AQ - Antartide 1
BB - Barbados 1
BE - Belgio 1
BN - Brunei Darussalam 1
CY - Cipro 1
DO - Repubblica Dominicana 1
GE - Georgia 1
KW - Kuwait 1
LU - Lussemburgo 1
LV - Lettonia 1
Totale 11.582
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Città #
Dallas 962
Santa Clara 867
Singapore 816
Dublin 400
Chandler 383
Jacksonville 332
San Jose 323
Moscow 274
Abidjan 238
Ashburn 206
Beijing 157
Boardman 148
Amsterdam 120
Catania 112
Hefei 110
Nanjing 108
Cambridge 106
Chicago 106
Lawrence 106
Civitanova Marche 105
Andover 103
Lauterbourg 101
Los Angeles 101
Toronto 96
Seoul 93
Dong Ket 86
Council Bluffs 63
Des Moines 56
Hanoi 56
Ho Chi Minh City 55
Dakar 53
Milan 52
Helsinki 47
Palermo 42
Hong Kong 41
San Mateo 39
New York 37
São Paulo 37
Wilmington 36
Columbus 35
Lagos 35
The Dalles 33
Hebei 31
Saint Petersburg 30
Nanchang 29
Shenyang 28
Changsha 26
Redondo Beach 26
Tianjin 24
Ottawa 22
Nuremberg 20
Buffalo 19
Jiaxing 19
Brno 18
Munich 18
Chennai 17
Orem 16
Rome 16
Tremestieri Etneo 16
Abuja 15
Brooklyn 15
New Taipei City 15
Messina 14
Rio de Janeiro 14
Dhaka 13
Montreal 13
Brasília 12
Bengaluru 11
Tokyo 11
Cotonou 10
Marseille 10
Porto Alegre 10
Warsaw 10
Biên Hòa 9
Cairo 9
London 9
Monte San Vito 9
Naples 9
Seattle 9
Stockholm 9
Auckland 8
Boston 8
Delft 8
Denver 8
Haiphong 8
Liberty Lake 8
Sortino 8
Turin 8
Amman 7
Belo Horizonte 7
Hangzhou 7
Jinan 7
Mumbai 7
Nakamaru 7
Poplar 7
Port Harcourt 7
Zhengzhou 7
Duncan 6
Falls Church 6
Grafing 6
Totale 8.032
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Nome #
A 3- V, 72-μ W and 0.042-mm2 Active-Area Dynamic Comparator in Flexible TFT Technology 206
Design guidelines of CMOS class-AB output stages: a tutorial 205
A 1-V CMOS Output Stage with High Linearity 204
A 28-nm CMOS 60-GHz LNA for OOK Low-Power Receivers 198
1.2-V CMOS op-amp with a dynamically biased output stage 185
A Clock Boosted Charge Pump with Reduced Rise Time 182
1.5V power supply CMOS voltage squarer 174
A Novel Clock Gating Approach for the Design of Low-Power Linear Feedback Shift Registers 172
A 1.5 CMOS Voltage Multiplier 168
A 50-mA 1-nF Low-Voltage Low-Dropout Voltage Regulator for SoC Applications 162
Dynamic-biased capacitor-free NMOS LDO voltage regulator 154
1V CMOS output stage with excellent linearity 151
A New Method for Harmonic Distortion Analysis in Class-AB Stages 149
An Accurate Ultra-Compact I–V Model for Nanometer MOS Transistors With Applications on Digital Circuits 143
A gm/ID-Based Design Strategy for IoT and Ultra-Low-Power OTAs with Fast-Settling and Large Capacitive Loads 137
High-Drive and Linear CMOS Class-AB Pseudo-Differential Amplifier 136
Analysis and optimization of a novel CMOS multiplier 135
Robust design of CMOS amplifiers oriented to settling-time specification 131
Autonomous Energy-Efficient Wireless Sensor Network Platform for Home/Office Automation 131
A Biasing Approach to design Ultra-Low-Power Standard-Cell-Based Analog Building Blocks for Nanometer SoCs 130
A 28-nm CMOS Low-Power/Low-Voltage 60-GHz LNA for High-Speed Communication 129
Integrated Quenching-and-Reset Circuit for Single-Photon Avalanche Diodes 121
A 5 mW 28 nm CMOS Low-Noise Amplifier with Transformer-Based Electrostatic Discharge Protection for 60 GHz Applications 120
Theoretical and experimental study of the role of cell-cell dipole interaction in dielectrophoretic devices: application to polynomial electrodes 120
Introduzione ai Convertitori A/D del tipo Sigma-Delta 120
Introduzione ai Dispositivi Elettronici 118
A Low-Voltage Low-Power Voltage Reference Based on Subthreshold MOSFETs 118
Optimized Charge Pump with Clock Booster for Reduced Rise Time or Silicon Area 117
A Fuzzy A/D Converter by Means of Current-Mode Approach 116
Approach to the design of low-voltage SC filters 115
A Detailed Analysis of Power-Supply Noise Attenuation in Bandgap Voltage References 114
Class-AB CMOS output stages suitable for low-voltage amplifiers in nanometer technologies 113
A Fuzzy Controller for Step-Up DC/DC Converters 112
Fractional Order Differ-Integral Operator in Integrated Technology 108
Device Modeling for Digital Circuits 107
An approach to test the open-loop parameters of feedback amplifiers 107
Guidelines for Designing Class-AB Output Stages 106
Behavioral modeling of statistical phenomena of single-photon avalanche diodes 105
High-dimensional dynamics in a single-transistor oscillator containing Feynman-Sierpiński resonators: Effect of fractal depth and irregularity 105
Three-Stage Dynamic-Biased CMOS Amplifier With a Robust Optimization of the Settling Time 104
Switched capacitor compatible minimum-maximum function 103
Power Supply Rejection of Widlar Bandgap Voltage Reference 101
Design and Comparison of Very Low-Voltage CMOS Output Stages 100
Robust Miller Compensation With Current Amplifiers Applied to LDO Voltage Regulator 100
A new method for evaluating harmonic distortion in push-pull output stages 100
Simple and Accurate Model for the Propagation Delay in MCML Gates 99
A fuzzy membership function circuit in SC technique 98
An Approach to the Design of Low-Voltage SC Filters 98
CMRR frequency response of CMOS operational transconductance amplifiers 98
Hybrid Full Adders: Optimized Design, Critical Review and Comparison in the Energy-Delay Space 97
Analysis and Comparison in the Energy-Delay Space of Nanometer CMOS One-Bit Full-Adders 96
A New Topology for the Implementation of Analog Maximum and Minimum Functions 96
Resistance of Feedback Amplifiers: A Novel Representation 95
Analysis and Optimization of a Low-Voltage Class-AB Output Stage 95
A Three-Stage Operational Transconductance Amplifier in TFT Flexible-Substrate Process 94
Resolution of a Current-Mode Algorithmic Analog-to-Digital Converter 94
Design of Three-Stage OTA Based on Settling-Time Requirements Including Large and Small Signal Behavior 94
HIGH–DRIVE CMOS CURRENT–FEEDBACK OPAMP 93
Study of the role of particle-particle dipole interaction in dielectrophoretic devices for biomarkers identification 93
Design of low-voltage low-power SC filters for high-frequency applications 92
Design of CMOS three-stage amplifiers for near-to-minimum settling-time 92
An ultra-compact MOS model in nanometer technologies 91
High-linear class AB transconductor for high-frequency applications 91
Exploiting the High-Frequency Performance of Low-Voltage Low-Power SC Filters 91
Sample frequency effects on a new SC realization of Fractional Order Integrator 90
A switched-capacitor compatible membership function block 89
An efficient fuzzy controller architecture in SC technique 88
Inverter transfer curves and SRAM noise margin evaluation based on an ultra-compact MOS model 87
Analysis, modelling and optimization of a gain boosted telescopic amplifier 86
Non-Inverting Class-AB CMOS Output Stage for Driving High-Capacitive Loads 86
A Novel 1.5-V CMOS Mixer 85
Design of CMOS OTAs with Settling-Time Constraints 85
Analysis and optimization of gain-boosted telescopic amplifiers 84
Frequency Behaviour of CMRR in One-Stage CMOS OTA 83
Verilog-a Modeling of SPAD Statistical Phenomena 82
Settling-time oriented OTA design through the approximation of the ideal delay 82
In-Depth Analysis of Pole-Zero Compensations in CMOS Operational Transconductance Amplifiers 82
A Novel Method for Determining Open-Loop Parameters in Feedback Amplifiers 80
Techniques for evaluating harmonic distortion in class-AB output stages: A tutorial 80
A simple extraction procedure for determining the electrical parameters in Silicon Photomultipliers 79
LDO Compensation Strategy based on Current Buffer/Amplifiers 78
Logic Gates Dynamic Modeling by Means of an Ultra-Compact MOS Model 77
On-chip low drop-out voltage regulator with NMOS power transistor and dynamic biasing technique 77
Statistical Analysis of CMOS Current Reference 77
Behavioral model of silicon photo-multipliers suitable for transistor-level circuit simulation 77
Statistical analysis of the resolution in a current-mode ADC 76
A Novel High-speed Cascode Current Mirror Compensation 76
A Novel CMOS Voltage Squarer 76
Comparison of Methods for Predicting Distortion in Class-AB Stages 76
Two-Stage OTA Design Based on Settling-Time Constraints 75
NMOS Low Drop-Out Regulator with Dynamic Biasing 75
Analysis of power supply noise attenuation in a PTAT current source 75
Statistical modelling and design guidelines of CMOS current references 75
Design Methodology of the Output Power Stage of a Step-Down DC-DC Converter 74
Compensation strategy for high-speed three-stage switched-capacitor amplifiers 74
Detailed Frequency Analysis of Power Supply Rejection in Brokaw Bandgap 74
VLSI Implementation of a Double-Layer Single Cell RD-CNN for Motion Control 74
Design of three-stage OTAs from settling-time and slew-rate constraints 74
A new voltage reference topology based on subthreshold MOSFETs 73
Theoretical and experimental study of the kinetics of particle chains near electrodes in dielectrophoretic devices 73
Totale 10.683
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Categoria #
all - tutte 36.312
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 36.312
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/2021154 0 0 0 0 0 0 0 0 0 0 47 107
2021/2022756 99 110 4 11 120 3 109 19 71 6 29 175
2022/20231.264 111 65 20 105 101 221 8 247 318 8 37 23
2023/2024908 42 257 30 23 12 80 46 15 16 150 128 109
2024/20252.580 123 290 129 175 628 362 91 110 126 248 138 160
2025/20264.891 310 300 1.075 340 671 828 540 150 389 284 4 0
Totale 11.919