IRIS
GIUSTOLISI, Gianluca
 Distribuzione geografica
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Continente #
NA - Nord America 5.105
AS - Asia 2.929
EU - Europa 2.852
SA - Sud America 504
AF - Africa 411
OC - Oceania 31
Continente sconosciuto - Info sul continente non disponibili 7
AN - Antartide 1
Totale 11.840
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Nazione #
US - Stati Uniti d'America 4.904
SG - Singapore 1.404
CN - Cina 807
IT - Italia 741
RU - Federazione Russa 704
IE - Irlanda 416
BR - Brasile 406
UA - Ucraina 294
VN - Vietnam 270
CI - Costa d'Avorio 238
FR - Francia 164
CA - Canada 161
NL - Olanda 144
KR - Corea 94
IN - India 77
DE - Germania 76
GB - Regno Unito 71
NG - Nigeria 57
HK - Hong Kong 56
SE - Svezia 56
FI - Finlandia 55
SN - Senegal 53
BD - Bangladesh 42
AR - Argentina 40
JP - Giappone 27
CH - Svizzera 26
TW - Taiwan 24
MX - Messico 23
CZ - Repubblica Ceca 18
PL - Polonia 18
AU - Australia 17
IQ - Iraq 17
AT - Austria 15
PK - Pakistan 15
NZ - Nuova Zelanda 14
EG - Egitto 13
TR - Turchia 13
EC - Ecuador 12
ES - Italia 11
UZ - Uzbekistan 11
BJ - Benin 10
VE - Venezuela 10
ID - Indonesia 9
PE - Perù 9
ZA - Sudafrica 9
CL - Cile 7
CO - Colombia 7
JO - Giordania 7
PH - Filippine 7
PY - Paraguay 7
DZ - Algeria 6
EU - Europa 6
KE - Kenya 6
MA - Marocco 6
SA - Arabia Saudita 6
TN - Tunisia 6
ET - Etiopia 5
GR - Grecia 5
NP - Nepal 5
AE - Emirati Arabi Uniti 4
BY - Bielorussia 4
IL - Israele 4
JM - Giamaica 4
LB - Libano 4
MD - Moldavia 4
MY - Malesia 4
TH - Thailandia 4
AZ - Azerbaigian 3
BO - Bolivia 3
KZ - Kazakistan 3
LT - Lituania 3
NO - Norvegia 3
RO - Romania 3
BG - Bulgaria 2
CR - Costa Rica 2
DK - Danimarca 2
EE - Estonia 2
GA - Gabon 2
HN - Honduras 2
HR - Croazia 2
HU - Ungheria 2
IR - Iran 2
KG - Kirghizistan 2
MT - Malta 2
NI - Nicaragua 2
OM - Oman 2
RS - Serbia 2
TT - Trinidad e Tobago 2
UY - Uruguay 2
AL - Albania 1
AQ - Antartide 1
BB - Barbados 1
BE - Belgio 1
BN - Brunei Darussalam 1
CY - Cipro 1
DO - Repubblica Dominicana 1
GE - Georgia 1
GT - Guatemala 1
KW - Kuwait 1
LU - Lussemburgo 1
Totale 11.830
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Città #
Dallas 965
Santa Clara 872
Singapore 822
Dublin 400
Chandler 383
San Jose 347
Jacksonville 332
Moscow 274
Abidjan 238
Ashburn 216
Beijing 167
Boardman 148
Amsterdam 120
Catania 114
Hefei 110
Nanjing 108
Chicago 107
Cambridge 106
Lawrence 106
Los Angeles 106
Civitanova Marche 105
Andover 103
Lauterbourg 101
Toronto 98
Seoul 93
Dong Ket 86
Council Bluffs 63
Des Moines 56
Hanoi 56
Ho Chi Minh City 55
Milan 54
Dakar 53
Helsinki 47
Hong Kong 46
Palermo 44
New York 40
San Mateo 39
São Paulo 37
Wilmington 36
Columbus 35
Lagos 35
The Dalles 33
Hebei 31
Saint Petersburg 30
Nanchang 29
Shenyang 28
Changsha 26
Redondo Beach 26
Tianjin 24
Ottawa 22
Rome 22
Buffalo 20
Nuremberg 20
Jiaxing 19
Orem 19
Brno 18
Munich 18
Brooklyn 17
Chennai 17
Naples 16
Tremestieri Etneo 16
Abuja 15
Montreal 15
New Taipei City 15
Messina 14
Rio de Janeiro 14
Dhaka 13
Bengaluru 12
Brasília 12
Tokyo 12
Warsaw 12
Cotonou 10
London 10
Marseille 10
Porto Alegre 10
Biên Hòa 9
Cairo 9
Monte San Vito 9
Seattle 9
Stockholm 9
Turin 9
Auckland 8
Boston 8
Delft 8
Denver 8
Haiphong 8
Hangzhou 8
Liberty Lake 8
Mexico City 8
Sortino 8
Amman 7
Belo Horizonte 7
Houston 7
Jinan 7
Mumbai 7
Nakamaru 7
Poplar 7
Port Harcourt 7
Washington 7
Zhengzhou 7
Totale 8.144
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Nome #
Design guidelines of CMOS class-AB output stages: a tutorial 215
A 3- V, 72-μ W and 0.042-mm2 Active-Area Dynamic Comparator in Flexible TFT Technology 210
A 1-V CMOS Output Stage with High Linearity 208
A 28-nm CMOS 60-GHz LNA for OOK Low-Power Receivers 202
1.2-V CMOS op-amp with a dynamically biased output stage 189
A Clock Boosted Charge Pump with Reduced Rise Time 187
A Novel Clock Gating Approach for the Design of Low-Power Linear Feedback Shift Registers 182
1.5V power supply CMOS voltage squarer 176
A 1.5 CMOS Voltage Multiplier 171
A 50-mA 1-nF Low-Voltage Low-Dropout Voltage Regulator for SoC Applications 166
1V CMOS output stage with excellent linearity 155
Dynamic-biased capacitor-free NMOS LDO voltage regulator 154
A 28-nm CMOS Low-Power/Low-Voltage 60-GHz LNA for High-Speed Communication 153
A New Method for Harmonic Distortion Analysis in Class-AB Stages 149
An Accurate Ultra-Compact I–V Model for Nanometer MOS Transistors With Applications on Digital Circuits 144
A gm/ID-Based Design Strategy for IoT and Ultra-Low-Power OTAs with Fast-Settling and Large Capacitive Loads 143
High-Drive and Linear CMOS Class-AB Pseudo-Differential Amplifier 138
A Biasing Approach to design Ultra-Low-Power Standard-Cell-Based Analog Building Blocks for Nanometer SoCs 136
Analysis and optimization of a novel CMOS multiplier 135
Autonomous Energy-Efficient Wireless Sensor Network Platform for Home/Office Automation 133
Robust design of CMOS amplifiers oriented to settling-time specification 131
A 5 mW 28 nm CMOS Low-Noise Amplifier with Transformer-Based Electrostatic Discharge Protection for 60 GHz Applications 122
Integrated Quenching-and-Reset Circuit for Single-Photon Avalanche Diodes 121
Theoretical and experimental study of the role of cell-cell dipole interaction in dielectrophoretic devices: application to polynomial electrodes 121
A Low-Voltage Low-Power Voltage Reference Based on Subthreshold MOSFETs 121
Introduzione ai Convertitori A/D del tipo Sigma-Delta 121
A Detailed Analysis of Power-Supply Noise Attenuation in Bandgap Voltage References 120
Introduzione ai Dispositivi Elettronici 118
Optimized Charge Pump with Clock Booster for Reduced Rise Time or Silicon Area 118
Class-AB CMOS output stages suitable for low-voltage amplifiers in nanometer technologies 118
A Fuzzy A/D Converter by Means of Current-Mode Approach 117
Approach to the design of low-voltage SC filters 115
A Fuzzy Controller for Step-Up DC/DC Converters 114
Guidelines for Designing Class-AB Output Stages 112
Fractional Order Differ-Integral Operator in Integrated Technology 109
An approach to test the open-loop parameters of feedback amplifiers 109
Behavioral modeling of statistical phenomena of single-photon avalanche diodes 108
Device Modeling for Digital Circuits 108
High-dimensional dynamics in a single-transistor oscillator containing Feynman-Sierpiński resonators: Effect of fractal depth and irregularity 107
Three-Stage Dynamic-Biased CMOS Amplifier With a Robust Optimization of the Settling Time 104
A Three-Stage Operational Transconductance Amplifier in TFT Flexible-Substrate Process 103
Switched capacitor compatible minimum-maximum function 103
Design and Comparison of Very Low-Voltage CMOS Output Stages 103
Power Supply Rejection of Widlar Bandgap Voltage Reference 101
Simple and Accurate Model for the Propagation Delay in MCML Gates 100
Robust Miller Compensation With Current Amplifiers Applied to LDO Voltage Regulator 100
A new method for evaluating harmonic distortion in push-pull output stages 100
Hybrid Full Adders: Optimized Design, Critical Review and Comparison in the Energy-Delay Space 99
A fuzzy membership function circuit in SC technique 99
Analysis and Comparison in the Energy-Delay Space of Nanometer CMOS One-Bit Full-Adders 98
Resistance of Feedback Amplifiers: A Novel Representation 98
An Approach to the Design of Low-Voltage SC Filters 98
CMRR frequency response of CMOS operational transconductance amplifiers 98
Analysis and Optimization of a Low-Voltage Class-AB Output Stage 97
HIGH–DRIVE CMOS CURRENT–FEEDBACK OPAMP 96
A New Topology for the Implementation of Analog Maximum and Minimum Functions 96
Design of Three-Stage OTA Based on Settling-Time Requirements Including Large and Small Signal Behavior 95
High-linear class AB transconductor for high-frequency applications 94
Resolution of a Current-Mode Algorithmic Analog-to-Digital Converter 94
Study of the role of particle-particle dipole interaction in dielectrophoretic devices for biomarkers identification 93
A switched-capacitor compatible membership function block 92
Design of low-voltage low-power SC filters for high-frequency applications 92
Design of CMOS three-stage amplifiers for near-to-minimum settling-time 92
An ultra-compact MOS model in nanometer technologies 91
Sample frequency effects on a new SC realization of Fractional Order Integrator 91
Exploiting the High-Frequency Performance of Low-Voltage Low-Power SC Filters 91
An efficient fuzzy controller architecture in SC technique 89
Inverter transfer curves and SRAM noise margin evaluation based on an ultra-compact MOS model 87
Analysis, modelling and optimization of a gain boosted telescopic amplifier 87
A Novel 1.5-V CMOS Mixer 86
Non-Inverting Class-AB CMOS Output Stage for Driving High-Capacitive Loads 86
A Comparative Analysis of 60-GHz LNAs for Low-Power mm-Wave Receivers 85
Design of CMOS OTAs with Settling-Time Constraints 85
Frequency Behaviour of CMRR in One-Stage CMOS OTA 84
Analysis and optimization of gain-boosted telescopic amplifiers 84
In-Depth Analysis of Pole-Zero Compensations in CMOS Operational Transconductance Amplifiers 83
Verilog-a Modeling of SPAD Statistical Phenomena 82
Settling-time oriented OTA design through the approximation of the ideal delay 82
Techniques for evaluating harmonic distortion in class-AB output stages: A tutorial 81
A simple extraction procedure for determining the electrical parameters in Silicon Photomultipliers 80
A Novel Method for Determining Open-Loop Parameters in Feedback Amplifiers 80
Statistical Analysis of CMOS Current Reference 80
LDO Compensation Strategy based on Current Buffer/Amplifiers 79
On-chip low drop-out voltage regulator with NMOS power transistor and dynamic biasing technique 79
A Novel CMOS Voltage Squarer 78
Behavioral model of silicon photo-multipliers suitable for transistor-level circuit simulation 78
Logic Gates Dynamic Modeling by Means of an Ultra-Compact MOS Model 77
Statistical analysis of the resolution in a current-mode ADC 76
A Novel High-speed Cascode Current Mirror Compensation 76
Analysis of power supply noise attenuation in a PTAT current source 76
Comparison of Methods for Predicting Distortion in Class-AB Stages 76
Compensation strategy for high-speed three-stage switched-capacitor amplifiers 75
Two-Stage OTA Design Based on Settling-Time Constraints 75
NMOS Low Drop-Out Regulator with Dynamic Biasing 75
VLSI Implementation of a Double-Layer Single Cell RD-CNN for Motion Control 75
Statistical modelling and design guidelines of CMOS current references 75
Design of three-stage OTAs from settling-time and slew-rate constraints 75
Design Methodology of the Output Power Stage of a Step-Down DC-DC Converter 74
Detailed Frequency Analysis of Power Supply Rejection in Brokaw Bandgap 74
A new voltage reference topology based on subthreshold MOSFETs 73
Totale 10.881
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Categoria #
all - tutte 38.506
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 38.506
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/2021107 0 0 0 0 0 0 0 0 0 0 0 107
2021/2022756 99 110 4 11 120 3 109 19 71 6 29 175
2022/20231.264 111 65 20 105 101 221 8 247 318 8 37 23
2023/2024908 42 257 30 23 12 80 46 15 16 150 128 109
2024/20252.580 123 290 129 175 628 362 91 110 126 248 138 160
2025/20265.142 310 300 1.075 340 671 828 540 150 389 284 180 75
Totale 12.170