Errors limiting the resolution of current-mode algorithmic analog-to-digital converters are mainly related to current mirror operation. While systematic errors can be minimized by proper circuit techniques, random sources are unavoidable. In this paper a statistical analysis of the resolution of a typical converter is carried out taking into account process tolerances. To support the analysis, a 4-bit ADC, realized in a 0.35-mum CMOS technology, was exhaustively simulated. Results were found to be in excellent agreement with theoretical derivations.
|Titolo:||Resolution of a Current-Mode Algorithmic Analog-to-Digital Converter|
|Data di pubblicazione:||2002|
|Appare nelle tipologie:||1.1 Articolo in rivista|