In this paper a three-stage dynamic-biased CMOS amplifier is designed with a robust optimization of its settling-time performance. The methodology studies the stability of a third order system through the so-called “separation factors” and analyzes the settling time performance through the use of contour plots, in order to define a suitable design strategy. The approach is experimentally validated through the design of a three-stage amplifier with a new compensation network. Monte Carlo simulations as well as experimental results on an integrated prototype demonstrate the validity of the proposed method.
|Titolo:||Three-Stage Dynamic-Biased CMOS Amplifier With a Robust Optimization of the Settling Time|
|Data di pubblicazione:||2015|
|Citazione:||Three-Stage Dynamic-Biased CMOS Amplifier With a Robust Optimization of the Settling Time / Giustolisi G; Palumbo G. - In: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS. - ISSN 1549-8328. - 62:11(2015), pp. 2641-2651.|
|Appare nelle tipologie:||1.1 Articolo in rivista|