This paper presents an efficient solution to reduce the power consumption of the popular linear feedback shift register by exploiting the gated clock approach. The power reduction with respect to other gated clock schemes is obtained by an efficient implementation of the logic gates and properly reducing the number of XOR gates in the feedback network. Transistor level simulations are performed by using standard cells in a 28-nm FD-SOI CMOS technology and a 300-MHz clock. Simulation results show a power reduction with respect to traditional implementations, which reaches values higher than 30%.

A Novel Clock Gating Approach for the Design of Low-Power Linear Feedback Shift Registers

Giustolisi, G
;
Mita, R;Palumbo, G;Scotti, G
2022

Abstract

This paper presents an efficient solution to reduce the power consumption of the popular linear feedback shift register by exploiting the gated clock approach. The power reduction with respect to other gated clock schemes is obtained by an efficient implementation of the logic gates and properly reducing the number of XOR gates in the feedback network. Transistor level simulations are performed by using standard cells in a 28-nm FD-SOI CMOS technology and a 300-MHz clock. Simulation results show a power reduction with respect to traditional implementations, which reaches values higher than 30%.
Logic gates
Low power electronics
Power demand
Topology
Linear feedback shift registers
Standards
Ciphers
Complementary pass-transistor logic (CPL)
gated clock
linear feedback shift register (LFSR)
low-power design
transmission gate (TG)
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.11769/541619
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