Hybrid Full Adders: Optimized Design, Critical Review and Comparison in the Energy-Delay Space

In this paper, we design and compare seven meaningful hybrid one-bit full adders topologies that are optimized in terms of energy-delay trade-offs to operate in multibit ripple carry adders. The goal is to provide the designer with a simple and powerful approach for choosing the best topology for a given power budget, speed performance, or any combination of both. The design and comparison deal with 4-bit and 8-bit ripple carry adders and exploit the derivation of the energy-efficient curves in the energy-delay space. To do so, first we define the procedures to obtain energy consumption and propagation delay by simulating a ripple carry adder designed at a transistor level. Then, we introduce a design methodology to optimize a ripple carry adder by minimizing some significant figures-of-merit in terms of energy-delay trade-offs. The comparison of the energy-efficient curves allows us to make a simple and effective comparison as well as to identify the best one-bit full adder topologies.