A novel CMOS voltage multiplier is proposed which is based on MOS transistors in the saturation region and uses a resistor load. A pencil-and-paper optimized design procedure and a detailed analysis of second-order non-idealities which affect the multiplier core are given. The circuit has been designed with a 1.2 mum CMOS process setting a 3V power supply and simulations have been performed to validate results. Copyright (C) 2001 John Wiley & Sons, Ltd.

Analysis and optimization of a novel CMOS multiplier

GIUSTOLISI, Gianluca;PALMISANO, Giuseppe;PALUMBO, Gaetano
2001

Abstract

A novel CMOS voltage multiplier is proposed which is based on MOS transistors in the saturation region and uses a resistor load. A pencil-and-paper optimized design procedure and a detailed analysis of second-order non-idealities which affect the multiplier core are given. The circuit has been designed with a 1.2 mum CMOS process setting a 3V power supply and simulations have been performed to validate results. Copyright (C) 2001 John Wiley & Sons, Ltd.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/20.500.11769/10238
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