A novel CMOS voltage multiplier is proposed which is based on MOS transistors in the saturation region and uses a resistor load. A pencil-and-paper optimized design procedure and a detailed analysis of second-order non-idealities which affect the multiplier core are given. The circuit has been designed with a 1.2 mum CMOS process setting a 3V power supply and simulations have been performed to validate results. Copyright (C) 2001 John Wiley & Sons, Ltd.
|Titolo:||Analysis and optimization of a novel CMOS multiplier|
|Data di pubblicazione:||2001|
|Citazione:||Analysis and optimization of a novel CMOS multiplier / Giustolisi G; Palmisano G; Palumbo G. - In: INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS. - ISSN 0098-9886. - 29:3(2001), pp. 321-330.|
|Appare nelle tipologie:||1.1 Articolo in rivista|