A low-voltage low drop-out (LDO) voltage regulator is proposed. It is based on an NMOS output stage and exploits dynamic biasing for obtaining low-voltage (1.2 V) and low drop-out (200 mV) features. It does not require any external compensation capacitor and is able to deliver 50 mA with capacitive loads up to 10 nF. The circuit topology is discussed and experimental results are given.
Dynamic-biased capacitor-free NMOS LDO voltage regulator
GIUSTOLISI, Gianluca;PALUMBO, Gaetano
2009-01-01
Abstract
A low-voltage low drop-out (LDO) voltage regulator is proposed. It is based on an NMOS output stage and exploits dynamic biasing for obtaining low-voltage (1.2 V) and low drop-out (200 mV) features. It does not require any external compensation capacitor and is able to deliver 50 mA with capacitive loads up to 10 nF. The circuit topology is discussed and experimental results are given.File in questo prodotto:
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