In this paper an improved Dickson charge pump topology exploiting a clock boosting is presented. An accurate while simple theoretical model for the dynamic behavior of the charge pump is carried out. Analytical comparison with the traditional Dickson charge pump reveals that the proposed solution can achieve a rise time or area reduction between 10% and 60% at the cost of a slight circuit complexity. Finally, simulation results using a 65-nm CMOS technology show the accuracy of the analytical model as well as the advantages of the proposed solution.
|Titolo:||Optimized Charge Pump with Clock Booster for Reduced Rise Time or Silicon Area|
|Data di pubblicazione:||Being printed|
|Appare nelle tipologie:||1.1 Articolo in rivista|