In this paper, an ultra-compact model for nanometer CMOS transistors, suitable for the analysis of digital circuits, is proposed. Starting from modified and more accurate versions of classical compact models, an extremely simple one (nine parameters and piecewise linear $I_{D}$ versus $V_{{rm DS}}$ relationships in both triode and saturation) is extracted. All the main physical effects that are predominant in nanometer technologies are included and the model is shown to allow an accurate and quick estimation of parameters such as delay or dc transfer curves. Simulation results are extracted in a 65-nm CMOS technology.
An Accurate Ultra-Compact I–V Model for Nanometer MOS Transistors With Applications on Digital Circuits
GIUSTOLISI, Gianluca;PALUMBO, Gaetano
2012-01-01
Abstract
In this paper, an ultra-compact model for nanometer CMOS transistors, suitable for the analysis of digital circuits, is proposed. Starting from modified and more accurate versions of classical compact models, an extremely simple one (nine parameters and piecewise linear $I_{D}$ versus $V_{{rm DS}}$ relationships in both triode and saturation) is extracted. All the main physical effects that are predominant in nanometer technologies are included and the model is shown to allow an accurate and quick estimation of parameters such as delay or dc transfer curves. Simulation results are extracted in a 65-nm CMOS technology.File | Dimensione | Formato | |
---|---|---|---|
R028 - An Accurate Ultra-Compact I–V Model for Nanometer MOS Transistors With Applications on Digital Circuits.pdf
solo gestori archivio
Tipologia:
Versione Editoriale (PDF)
Licenza:
Non specificato
Dimensione
1.14 MB
Formato
Adobe PDF
|
1.14 MB | Adobe PDF | Visualizza/Apri |
I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.