The authors propose a parallel architecture for neural network (NN) simulation in which the processing elements, based on digital signal processors, communicate through a common bus structure. The architecture offers high processing power and fault tolerance capabilities. These can be exploited by the use of dynamically reconfigurable devices in the communication interfaces. The architectural choices are discussed and a performance evaluation of the system is performed in order to assess its features.

ARTIFICIAL NEURAL NETWORKS ON A RECONFIGURABLE, FAULT-TOLERANT, MULTIPROCESSOR SYSTEM

CAVALIERI, Salvatore
;
DI STEFANO, Antonella;MIRABELLA, Orazio
1994

Abstract

The authors propose a parallel architecture for neural network (NN) simulation in which the processing elements, based on digital signal processors, communicate through a common bus structure. The architecture offers high processing power and fault tolerance capabilities. These can be exploited by the use of dynamically reconfigurable devices in the communication interfaces. The architectural choices are discussed and a performance evaluation of the system is performed in order to assess its features.
Artificial neural networks, Multi digital signal processor architecture, Neural network simulation
File in questo prodotto:
Non ci sono file associati a questo prodotto.

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/20.500.11769/11197
Citazioni
  • ???jsp.display-item.citation.pmc??? ND
  • Scopus 1
  • ???jsp.display-item.citation.isi??? 0
social impact