We present a compact model for the DC and small signal AC analysis of Organic Thin Film Transistors (OTFTs). The DC part of the model assumes that the electrical current injected in the OTFT is limited by the presence of a metal/organic semiconductor junction that, at source, acts as a reverse biased Schottky junction. By including this junction, modeled as a reverse biased gated diode at source, the DC model is able to reproduce the scaling of the electrical characteristics even for short channel devices. The small signal AC part of the model uses a transmission line approach in order to compute the impedances of the channel and parasitic regions of the device. The overlap capacitances and the presence of non-ideal metal/organic semiconductor junctions are taken in account as well and the model can be easily adapted to different device geometries. The model is particularly well suited for printed devices, often realized with large process tolerances, since it takes into consideration the presence of parasitic regions and their effect on the AC operation. The model has been validated on printed OTFTs using a pentace-derivative as organic semiconductor with a quite peculiar device layout. It has been fully implemented in Verilog-A programming language.

A DC and small signal AC model for organic thin film transistors including contact effects and non quasi static regime

FRASCA, MATTIA;
2017

Abstract

We present a compact model for the DC and small signal AC analysis of Organic Thin Film Transistors (OTFTs). The DC part of the model assumes that the electrical current injected in the OTFT is limited by the presence of a metal/organic semiconductor junction that, at source, acts as a reverse biased Schottky junction. By including this junction, modeled as a reverse biased gated diode at source, the DC model is able to reproduce the scaling of the electrical characteristics even for short channel devices. The small signal AC part of the model uses a transmission line approach in order to compute the impedances of the channel and parasitic regions of the device. The overlap capacitances and the presence of non-ideal metal/organic semiconductor junctions are taken in account as well and the model can be easily adapted to different device geometries. The model is particularly well suited for printed devices, often realized with large process tolerances, since it takes into consideration the presence of parasitic regions and their effect on the AC operation. The model has been validated on printed OTFTs using a pentace-derivative as organic semiconductor with a quite peculiar device layout. It has been fully implemented in Verilog-A programming language.
Organic thin film transistors; DC model; AC model; Contact effects; parasitic capacitance; Non-quasi static small signal model
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.11769/241127
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