The aim of this paper is to present a true random bit generator (TRBG) based on a memristive chaotic circuit and its implementation on Field Programmable Gate Array (FPGA) board. The proposed TRBG architecture makes use of a memristive canonical Chua's oscillator and a logistic map as entropy sources, while the XOR function is used for post-processing. The optimal parameter set for the chaotic systems has been chosen by carrying out numerical simulations of the system and adopting the scale index parameter to determine the degree of non-periodicity of the obtained bit streams. The proposed TRBG system has been then modeled and co-simulated on the Xilinx System Generator (XSG) platform and implemented on the Xilinx Kintex-7 KC705 FPGA Evaluation Board, obtaining experimental results in agreement with the expectations. Finally, the system has been validated with statistical analysis by using the NIST 800.22 statistical test suite.

A true random bit generator based on a memristive chaotic circuit: Analysis, design and FPGA implementation

Frasca, Mattia
2019

Abstract

The aim of this paper is to present a true random bit generator (TRBG) based on a memristive chaotic circuit and its implementation on Field Programmable Gate Array (FPGA) board. The proposed TRBG architecture makes use of a memristive canonical Chua's oscillator and a logistic map as entropy sources, while the XOR function is used for post-processing. The optimal parameter set for the chaotic systems has been chosen by carrying out numerical simulations of the system and adopting the scale index parameter to determine the degree of non-periodicity of the obtained bit streams. The proposed TRBG system has been then modeled and co-simulated on the Xilinx System Generator (XSG) platform and implemented on the Xilinx Kintex-7 KC705 FPGA Evaluation Board, obtaining experimental results in agreement with the expectations. Finally, the system has been validated with statistical analysis by using the NIST 800.22 statistical test suite.
Chaos; Chua's oscillator; FPGA; Logistic map; Memristor; True random bit generator; Mathematics (all)
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.11769/361946
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