An Integrated Approach to Optimize Power Device Performances by Means of Stress Engineering

In the present work it is shown how stress engineering can be used in semiconductor industry to improve Power MOSFET transistor’s performance beyond simple geometrical downscaling. The aim of this paper is to present an integrated methodology, coupling modelling and experimental results, focused on the structural optimization of a power device by means of final passivation mechanical stress tuning. The proposed approach is based on a Finite Element Model that describes and predicts the mechanical strain of a singulated power device (MOSFET) validated by the correlation with interferometric experimental warpage measurements (Topography and Deformation Measurements). Scope of the activity is to engineer Power Devices with reduced intrinsic stresses in order to optimize the reliability performances. Controlled stress into a single semiconductor crystal oriented substrate can be managed at manufacturing level by several methods, including the introduction of a layer on the top of the substrate or around the gate region. From the knowledge of the mechanical boundaries, as a function of temperature, it is possible to predict the stress conditions impacting on device fabrication and on reliability performances. Moreover, according to the piezoresistive model, it has been evaluated the electrical characteristics (on-resistance) in the operative working condition range. According to the proposed approach an optimized passivation layer solution has been proposed, simulated by Finite Element model and validated by experiments.