Current MultiProcessor System-on-Chips exploit the Network-on-Chip (NoC) design paradigm as a viable solution to get an efficient and scalable communication backbone. As the number of integrated cores keeps growing, alternatives to the multi-hop nature of NoCs like Wireless Networks-on-Chip (WiNoCs) have been proposed to provide a subset of network nodes with a wireless interface that enables long-range communications in a single hop. In this work, we propose the use of on-chip wireless communication on Multi-stage Interconnection Networks (MINs) based NoCs. After extending the well-known Noxim platform to support Wireless MINs architectures, we perform an extensive set of cycle-level estimation demonstrating that, while traditionally used in high-performance parallel computing, wireless-augmented MINs represent a very promising candidate for the applicability of on-chip radio communications technologies, with a noticeable improvement in both average delay and saturation point, at the cost of an estimated energy overhead ranging from 2.8 up to 18.4 in the case of 128 core nodes.
Implementing On-Chip Wireless Communication in Multi-stage Interconnection NoCs
Monteleone S.;Palesi M.;Patti D.
2020-01-01
Abstract
Current MultiProcessor System-on-Chips exploit the Network-on-Chip (NoC) design paradigm as a viable solution to get an efficient and scalable communication backbone. As the number of integrated cores keeps growing, alternatives to the multi-hop nature of NoCs like Wireless Networks-on-Chip (WiNoCs) have been proposed to provide a subset of network nodes with a wireless interface that enables long-range communications in a single hop. In this work, we propose the use of on-chip wireless communication on Multi-stage Interconnection Networks (MINs) based NoCs. After extending the well-known Noxim platform to support Wireless MINs architectures, we perform an extensive set of cycle-level estimation demonstrating that, while traditionally used in high-performance parallel computing, wireless-augmented MINs represent a very promising candidate for the applicability of on-chip radio communications technologies, with a noticeable improvement in both average delay and saturation point, at the cost of an estimated energy overhead ranging from 2.8 up to 18.4 in the case of 128 core nodes.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
