In this paper, a novel gate-level strategy for designing Carry-Select adders is proposed. The strategy is more general than the previously proposed techniques, and accounts for the dependence of multiplexer delay on its fan-out. Moreover the strategy is simple and systematic, and is helpful for designing Carry-Select adders with a pencil-and-paper approach. An approximate expression of the minimum delay achievable is derived to estimate performance before carrying out the design. The proposed strategy is validated in more than 1000 adders. Analysis confirms that the strategy leads to a delay which is minimal in most cases, and always within 5.7%. (C) 2010 Elsevier B.V. All rights reserved.
Optimized design of parallel carry-select adders
PALUMBO, Gaetano;
2011-01-01
Abstract
In this paper, a novel gate-level strategy for designing Carry-Select adders is proposed. The strategy is more general than the previously proposed techniques, and accounts for the dependence of multiplexer delay on its fan-out. Moreover the strategy is simple and systematic, and is helpful for designing Carry-Select adders with a pencil-and-paper approach. An approximate expression of the minimum delay achievable is derived to estimate performance before carrying out the design. The proposed strategy is validated in more than 1000 adders. Analysis confirms that the strategy leads to a delay which is minimal in most cases, and always within 5.7%. (C) 2010 Elsevier B.V. All rights reserved.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
