Capacitance detection is a universal transduction mechanism used in a wide variety of sensors and applications. It requires an electronic front-end converting the capacitance variation into another more convenient physical variable, ultimately determining the performance of the whole sensor. In this paper we present a comprehensive review of the different signal conditioning front-end topologies targeted in particular at sub-femtofarad resolution. Main design equations and analysis of the limits due to noise are reported in order to provide the designer with guidelines for choosing the most suitable topology according to the main design specifications, namely energy consumption, area occupation, measuring time and resolution. A data-driven comparison of the different solutions in literature is also carried out revealing that resolution, measuring time, area occupation and energy/conversion lower than 100 aF, 1 ms 0.1 mm2, and 100 pJ/conv. can be obtained by capacitance to digital topologies, which therefore allow to get the best compromise among all design specifications.
Sub-Femto-Farad Resolution Electronic Interfaces for Integrated Capacitive Sensors: A Review
Ferlito U.;Grasso A. D.
Co-primo
;Pennisi S.;
2020-01-01
Abstract
Capacitance detection is a universal transduction mechanism used in a wide variety of sensors and applications. It requires an electronic front-end converting the capacitance variation into another more convenient physical variable, ultimately determining the performance of the whole sensor. In this paper we present a comprehensive review of the different signal conditioning front-end topologies targeted in particular at sub-femtofarad resolution. Main design equations and analysis of the limits due to noise are reported in order to provide the designer with guidelines for choosing the most suitable topology according to the main design specifications, namely energy consumption, area occupation, measuring time and resolution. A data-driven comparison of the different solutions in literature is also carried out revealing that resolution, measuring time, area occupation and energy/conversion lower than 100 aF, 1 ms 0.1 mm2, and 100 pJ/conv. can be obtained by capacitance to digital topologies, which therefore allow to get the best compromise among all design specifications.File | Dimensione | Formato | |
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